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  • A processor has 4 cores
  • Each core has 2 - Hyper threads
  • Its clock frequency is 2 GHz
  • On average, an instruction needs 4 cpu cycles to execute on each hyperthread

How many instructions can it execute in one second? I need help as to which equations to use. I know that 1 GHz has 1 cpu cycle at 1 nano second so therefore the 2 GHz will do one cpu cycle in .5 nano seconds.

  • I think this is off here, try to check up other StackExchange forums like: [serverfault](http://serverfault.com/) or [superuser](http://superuser.com/) – CsBalazsHungary Mar 06 '14 at 09:20

2 Answers2

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Well, I'll get you started, but it's a basic math problem.

2Ghz - frequency, in [cycles/second]. 4 - instruction duration, in [cycles/ops].

So 2Ghz [cycles/second] / 4 [cycles/ops] = 0.5Ghz [ops/second]. Note that the cycles unit cancels out and this "feels right" because we're left with the units that are being asked for :)

Do similar math to account for the Hyper-threads and Cores - only it will be multiplication. (You can carry through the units, e.g. [ops*threads*cores/second], but they can be dropped in context of the answer which is asking for ops/second across all v-cores.)

user2864740
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  • This answer (and the question really) completely miss the whole concept of pipelining. – Nathan Binkert Mar 08 '14 at 06:05
  • @NathanBinkert While this is indeed a trivialized scenario, the question presumably comes from a textbook/exercise and provides the required information for the expected level of answer: "On *average*, an instruction needs 4 cpu cycles to execute on each hyperthread" – user2864740 Mar 08 '14 at 08:54
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    You're probably right. It's been a very long time since people build processors that were wholly consumed by one instruction at a time and had no pipelining. Especially machines that do simplistic (e.g. round-robin) hyperthreading. – Nathan Binkert Mar 12 '14 at 16:58
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This question is a bit incomplete. Just because, on average an instruction takes 4 cycles doesn't mean that a processor cannot work on more than one thing at a time. Instruction level parallelism (ILP) is had by employing concepts like super-scalar execution, pipelining and out-of-order execution mean that we have processors are capable of completing 4 instructions (or more) on every cycle. So the numbers you need are the processor frequency, the number of cores, and the number of instructions per second (IPC) that each core can sustain. Things like hyperthreading, caching, prefetching, etc. are just features that help the processor reach the IPC that it was designed for. Check out computer architecture books like Hennesy & Patterson's Computer Architecture: A Quantitative Approach. Generally ILP is covered in one of the first couple of chapters.

Nathan Binkert
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