display a random generated number on 7 segment

Question

I can only use one of the four 7-segment displays. If I comments this line of code led ledh(rn1_temp[7:4], segh_temp); , it will run well, even though with some warning message. But when I try to use two of them to display a 5-bit number, it gave me these two errors.

ERROR:MapLib:979 - LUT2 symbol "seg<2>1" (output signal=seg_2_OBUF) has input
signal "seg_5_OBUF" which will be trimmed. See Section 5 of the Map Report
File for details about why the input signal will become undriven.
ERROR:MapLib:978 - LUT2 symbol "seg<2>1" (output signal=seg_2_OBUF) has an
equation that uses input pin I0, which no longer has a connected signal.
Please ensure that all the pins used in the equation for this LUT have
signals that are not trimmed (see Section 5 of the Map Report File for
details on which signals were trimmed).

Do I need some slow clock or sth? I don't know what is the problem with this code. Any assistance will be appreciated.

module fivebit_RandomNumber (rst, clk, rn);//generate a 5-bit random number
input rst, clk;   
output reg [4:0] rn;

wire w14;
assign w14 = rn[1]^rn[4];


always @ (posedge clk)
if (~rst) 
    begin
        rn <= 5'b11111; 
end else
    begin 
        rn <= {rn[3],rn[2],rn[1],rn[0],w14};
    end

endmodule



module led(rn, seg);

input [3:0] rn;
output [7:0] seg;


reg [7:0] seg_temp;
always @ (*)
begin
case (rn)
    4'b0000 : seg_temp = 8'b00000011;
    4'b0001 : seg_temp = 8'b10011111;       //1
    4'b0010 : seg_temp = 8'b00100101;       //2
    4'b0011 : seg_temp = 8'b00001101;       //3
    4'b0100 : seg_temp = 8'b10011001;       //4
    4'b0101 : seg_temp = 8'b01001001;       //5 
    4'b0110 : seg_temp = 8'b01000001;       //6
    4'b0111 : seg_temp = 8'b00011111;       //7
    4'b1000 : seg_temp = 8'b00000001;       //8
    4'b1001 : seg_temp = 8'b00011001;       //9 
    4'b1010 : seg_temp = 8'b00010001;       //10
    4'b1011 : seg_temp = 8'b11000001;       //11
    4'b1100 : seg_temp = 8'b01100011;       //12
    4'b1101 : seg_temp = 8'b10000101;       //13
    4'b1110 : seg_temp = 8'b01100001;       //14
    4'b1111 : seg_temp = 8'b01110001;       //15
    default : seg_temp = 8'b11111111; 
endcase
end

assign seg = seg_temp;

endmodule


module display(clk, rst, btn, seg, anodes);

input clk, btn, rst;


output [7:0] seg;
output [3:0] anodes;


wire [4:0] imrn;

fivebit_RandomNumber frn (rst, clk, imrn);

reg enable;

always @ (posedge clk or negedge btn)
begin
if (~btn) 
begin
    enable = 1;
end
else 
begin
    enable = 0;
end
end

reg [7:0] rn1_temp;

always @ (*)
begin
if (enable)
begin
    rn1_temp = {0,0,0,imrn};
end
end


reg [3:0] anodes;

wire [7:0] segl_temp, segh_temp;
reg [7:0] seg_temp;


led ledh(rn1_temp[7:4], segh_temp);        //a problem in this line
led ledl(rn1_temp[3:0], segl_temp);

always @ (*)
begin
case (anodes)
    4'b1111 : anodes = 4'b1101;
    4'b1101 : anodes = 4'b1110;
    4'b1110 : anodes = 4'b1101;
    default : anodes = 4'b1111;
endcase
case (anodes)
    4'b1101 : seg_temp = segh_temp;
    4'b1110 : seg_temp = segl_temp;
    default : seg_temp = 8'b11111111;
endcase
end

assign seg = (&anodes) ? 8'b11111111 : seg_temp;


endmodule

The problem is in the last `always @*` that drives `anodes` and `seg_temp`. Since `anodes` is determined by `anodes` it infers complex latch logic, if it can even synthesize. It is not clear how you intend the two digests to share one display. As is, `anodes` will change whenever there is an updated to `rn1_temp` and will only updated one display regardless of the value change to `rn1_temp`. Please elaborate your intentions. — Greg, Mar 05 '14 at 00:19
Yes, thanks for your points. I was trying to multiplexing the displays. I changed that block of codes, by adding case statement on a `counter`, like a slow clock, not on `anodes` directly. Thanks again. I am just new in verilog, so needs time to get used to it. — n00d1es, Mar 05 '14 at 15:04

score 0 · Answer 1 · answered Mar 05 '14 at 19:17

Looks like you are trying to multiplex the seg output. Try changing the following:

output [7:0] seg;
output [3:0] anodes;

// ...
reg [3:0] anodes;
/// ...
reg [7:0] seg_temp;
/// ...

always @ (*)
begin
case (anodes)
    4'b1111 : anodes = 4'b1101;
    4'b1101 : anodes = 4'b1110;
    4'b1110 : anodes = 4'b1101;
    default : anodes = 4'b1111;
endcase
case (anodes)
    4'b1101 : seg_temp = segh_temp;
    4'b1110 : seg_temp = segl_temp;
    default : seg_temp = 8'b11111111;
endcase
end

assign seg = (&anodes) ? 8'b11111111 : seg_temp;

To:

output reg [7:0] seg;
output reg [3:0] anodes;

// ...

always @ (posedge clk)
begin
case (anodes)
    4'b1111 : anodes <= 4'b1101;
    4'b1101 : anodes <= 4'b1110;
    4'b1110 : anodes <= 4'b1101;
    default : anodes <= 4'b1111;
endcase
end

always @ (*)
begin
case (anodes)
    4'b1101 : seg = segh_temp;
    4'b1110 : seg = segl_temp;
    default : seg = 8'b11111111;
endcase
end

This way anodes is synchronously controlled by the clk and seg is still combination logic.

Synchronous assignments should use non-blocking (<=). Update your assignments to enable to non-blocking.

display a random generated number on 7 segment

1 Answers1