RTL simulation of FIFO module by Active HDL (on Lattice Diamond)

Question

I evaluate the FPGA on MachXO2 Breakout Board, which is manufactured by Lattice Semiconductor. Now I am trying RTL simulation of FIFO_DC module, which is generated by IPExpress.

I created a simple testbench for FIFO module. When I started Active-HDL from simulation wizard,I got following error message.

I cannot get any support from Lattice because this work is just my hobby, not my job. Could you give me an advice about this problem? Any help would be appreciated. Thanks in advance.

Error message on Active-HDL's console

ELAB2: Fatal Error: ELAB2_0036 Unresolved hierarchical reference to "PUR_INST.PURNET" from module "FifoTest_tb.fifo.FifoMacro_0_3" (module not found).

Sample HDL

[FifoTest_tb.v] --> testbench for FIFO module

`timescale 1ns/1ps

module FifoTest_tb();

parameter CLOCK_PERIOD = 10;
parameter LOOP_CYCLE = 100;
integer i;

reg [7:0] tb_data;
reg tb_ck;
reg tb_wen;
reg tb_ren;
reg tb_clr;
wire [7:0] tb_q;
wire tb_emp;
wire tb_full;
wire tb_aef;
wire tb_aff;


//module instantiation
FifoMacro fifo(
    .Data(tb_data),
    .WrClock(tb_ck),
    .RdClock(tb_ck),
    .WrEn(tb_wen),
    .RdEn(tb_ren),
    .Reset(tb_clr),
    .RPReset(tb_clr),
    .Q(tb_q),
    .Empty(tb_emp),
    .Full(tb_full),
    .AlmostEmpty(tb_aef),
    .AlmostFull(tb_aff)
    );

//Behavior 

always #(CLOCK_PERIOD/2) tb_ck = ~tb_ck;

initial begin
    tb_data = 0;
    tb_ck   = 0;
    tb_wen  = 0;
    tb_ren  = 0;
    tb_clr  = 1;

    @(negedge tb_ck) begin
        tb_clr <= 0;
        tb_wen <= 1;
    end 

    //Write cycle
    for(i=0; i<LOOP_CYCLE; i=i+1)begin
        @(negedge tb_ck) begin
            tb_data <= i % 256;
        end
    end


    //Write cycle
    @(negedge tb_ck) begin
        tb_wen <= 0;
        tb_ren <= 1;
    end

    for(i=0; i<LOOP_CYCLE; i=i+1)begin
        @(negedge tb_ck) begin
            tb_data <= i % 256;
        end
    end
    $stop;
    $finish;

end


endmodule





/* Verilog netlist generated by SCUBA Diamond_3.0_Production (94) */
/* Module Version: 5.5 */
/* C:\lscc\diamond\3.0\ispfpga\bin\nt\scuba.exe -w -n FifoMacro -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ebfifo -depth 4096 -width 8 -rwidth 8 -regout -resetmode ASYNC -reset_rel ASYNC -no_enable -pe 256 -pf 3840 -e  */
/* Tue Feb 25 21:38:17 2014 */

[FifoMacro.v] --> a file automatically generated by IPExpress (FIFO_DC module)

`timescale 1 ns / 1 ps
module FifoMacro (Data, WrClock, RdClock, WrEn, RdEn, Reset, RPReset, Q, 
    Empty, Full, AlmostEmpty, AlmostFull)/* synthesis NGD_DRC_MASK=1 */;
    input wire [7:0] Data;
    input wire WrClock;
    input wire RdClock;
    input wire WrEn;
    input wire RdEn;
    input wire Reset;
    input wire RPReset;
    output wire [7:0] Q;
    output wire Empty;
    output wire Full;
    output wire AlmostEmpty;
    output wire AlmostFull;

    wire Empty_int;
    wire Full_int;
    wire scuba_vhi;
    wire scuba_vlo;

    defparam FifoMacro_0_3.FULLPOINTER1 = "0b01111111111110" ;
    defparam FifoMacro_0_3.FULLPOINTER = "0b10000000000000" ;
    defparam FifoMacro_0_3.AFPOINTER1 = "0b01110111111110" ;
    defparam FifoMacro_0_3.AFPOINTER = "0b01111000000000" ;
    defparam FifoMacro_0_3.AEPOINTER1 = "0b00001000000010" ;
    defparam FifoMacro_0_3.AEPOINTER = "0b00001000000000" ;
    defparam FifoMacro_0_3.ASYNC_RESET_RELEASE = "ASYNC" ;
    defparam FifoMacro_0_3.GSR = "DISABLED" ;
    defparam FifoMacro_0_3.RESETMODE = "ASYNC" ;
    defparam FifoMacro_0_3.REGMODE = "OUTREG" ;
    defparam FifoMacro_0_3.CSDECODE_R = "0b11" ;
    defparam FifoMacro_0_3.CSDECODE_W = "0b11" ;
    defparam FifoMacro_0_3.DATA_WIDTH_R = 2 ;
    defparam FifoMacro_0_3.DATA_WIDTH_W = 2 ;
    FIFO8KB FifoMacro_0_3 (.DI0(scuba_vlo), .DI1(scuba_vlo), .DI2(Data[0]), 
        .DI3(scuba_vlo), .DI4(scuba_vlo), .DI5(Data[1]), .DI6(scuba_vlo), 
        .DI7(scuba_vlo), .DI8(scuba_vlo), .DI9(scuba_vlo), .DI10(scuba_vlo), 
        .DI11(Data[0]), .DI12(scuba_vlo), .DI13(scuba_vlo), .DI14(scuba_vlo), 
        .DI15(scuba_vlo), .DI16(scuba_vlo), .DI17(scuba_vlo), .CSW0(scuba_vhi), 
        .CSW1(scuba_vhi), .CSR0(RdEn), .CSR1(scuba_vhi), .FULLI(Full_int), 
        .EMPTYI(Empty_int), .WE(WrEn), .RE(scuba_vhi), .ORE(scuba_vhi), 
        .CLKW(WrClock), .CLKR(RdClock), .RST(Reset), .RPRST(RPReset), .DO0(Q[0]), 
        .DO1(Q[1]), .DO2(), .DO3(), .DO4(), .DO5(), .DO6(), .DO7(), .DO8(), 
        .DO9(), .DO10(), .DO11(), .DO12(), .DO13(), .DO14(), .DO15(), .DO16(), 
        .DO17(), .EF(Empty_int), .AEF(AlmostEmpty), .AFF(AlmostFull), .FF(Full_int));

    defparam FifoMacro_1_2.FULLPOINTER1 = "0b00000000000000" ;
    defparam FifoMacro_1_2.FULLPOINTER = "0b11111111111110" ;
    defparam FifoMacro_1_2.AFPOINTER1 = "0b00000000000000" ;
    defparam FifoMacro_1_2.AFPOINTER = "0b11111111111110" ;
    defparam FifoMacro_1_2.AEPOINTER1 = "0b00000000000000" ;
    defparam FifoMacro_1_2.AEPOINTER = "0b11111111111110" ;
    defparam FifoMacro_1_2.ASYNC_RESET_RELEASE = "ASYNC" ;
    defparam FifoMacro_1_2.GSR = "DISABLED" ;
    defparam FifoMacro_1_2.RESETMODE = "ASYNC" ;
    defparam FifoMacro_1_2.REGMODE = "OUTREG" ;
    defparam FifoMacro_1_2.CSDECODE_R = "0b11" ;
    defparam FifoMacro_1_2.CSDECODE_W = "0b11" ;
    defparam FifoMacro_1_2.DATA_WIDTH_R = 2 ;
    defparam FifoMacro_1_2.DATA_WIDTH_W = 2 ;
    FIFO8KB FifoMacro_1_2 (.DI0(scuba_vlo), .DI1(scuba_vlo), .DI2(Data[2]), 
        .DI3(scuba_vlo), .DI4(scuba_vlo), .DI5(Data[3]), .DI6(scuba_vlo), 
        .DI7(scuba_vlo), .DI8(scuba_vlo), .DI9(scuba_vlo), .DI10(scuba_vlo), 
        .DI11(Data[2]), .DI12(scuba_vlo), .DI13(scuba_vlo), .DI14(scuba_vlo), 
        .DI15(scuba_vlo), .DI16(scuba_vlo), .DI17(scuba_vlo), .CSW0(scuba_vhi), 
        .CSW1(scuba_vhi), .CSR0(RdEn), .CSR1(scuba_vhi), .FULLI(Full_int), 
        .EMPTYI(Empty_int), .WE(WrEn), .RE(scuba_vhi), .ORE(scuba_vhi), 
        .CLKW(WrClock), .CLKR(RdClock), .RST(Reset), .RPRST(RPReset), .DO0(Q[2]), 
        .DO1(Q[3]), .DO2(), .DO3(), .DO4(), .DO5(), .DO6(), .DO7(), .DO8(), 
        .DO9(), .DO10(), .DO11(), .DO12(), .DO13(), .DO14(), .DO15(), .DO16(), 
        .DO17(), .EF(), .AEF(), .AFF(), .FF());

    defparam FifoMacro_2_1.FULLPOINTER1 = "0b00000000000000" ;
    defparam FifoMacro_2_1.FULLPOINTER = "0b11111111111110" ;
    defparam FifoMacro_2_1.AFPOINTER1 = "0b00000000000000" ;
    defparam FifoMacro_2_1.AFPOINTER = "0b11111111111110" ;
    defparam FifoMacro_2_1.AEPOINTER1 = "0b00000000000000" ;
    defparam FifoMacro_2_1.AEPOINTER = "0b11111111111110" ;
    defparam FifoMacro_2_1.ASYNC_RESET_RELEASE = "ASYNC" ;
    defparam FifoMacro_2_1.GSR = "DISABLED" ;
    defparam FifoMacro_2_1.RESETMODE = "ASYNC" ;
    defparam FifoMacro_2_1.REGMODE = "OUTREG" ;
    defparam FifoMacro_2_1.CSDECODE_R = "0b11" ;
    defparam FifoMacro_2_1.CSDECODE_W = "0b11" ;
    defparam FifoMacro_2_1.DATA_WIDTH_R = 2 ;
    defparam FifoMacro_2_1.DATA_WIDTH_W = 2 ;
    FIFO8KB FifoMacro_2_1 (.DI0(scuba_vlo), .DI1(scuba_vlo), .DI2(Data[4]), 
        .DI3(scuba_vlo), .DI4(scuba_vlo), .DI5(Data[5]), .DI6(scuba_vlo), 
        .DI7(scuba_vlo), .DI8(scuba_vlo), .DI9(scuba_vlo), .DI10(scuba_vlo), 
        .DI11(Data[4]), .DI12(scuba_vlo), .DI13(scuba_vlo), .DI14(scuba_vlo), 
        .DI15(scuba_vlo), .DI16(scuba_vlo), .DI17(scuba_vlo), .CSW0(scuba_vhi), 
        .CSW1(scuba_vhi), .CSR0(RdEn), .CSR1(scuba_vhi), .FULLI(Full_int), 
        .EMPTYI(Empty_int), .WE(WrEn), .RE(scuba_vhi), .ORE(scuba_vhi), 
        .CLKW(WrClock), .CLKR(RdClock), .RST(Reset), .RPRST(RPReset), .DO0(Q[4]), 
        .DO1(Q[5]), .DO2(), .DO3(), .DO4(), .DO5(), .DO6(), .DO7(), .DO8(), 
        .DO9(), .DO10(), .DO11(), .DO12(), .DO13(), .DO14(), .DO15(), .DO16(), 
        .DO17(), .EF(), .AEF(), .AFF(), .FF());

    VHI scuba_vhi_inst (.Z(scuba_vhi));

    VLO scuba_vlo_inst (.Z(scuba_vlo));

    defparam FifoMacro_3_0.FULLPOINTER1 = "0b00000000000000" ;
    defparam FifoMacro_3_0.FULLPOINTER = "0b11111111111110" ;
    defparam FifoMacro_3_0.AFPOINTER1 = "0b00000000000000" ;
    defparam FifoMacro_3_0.AFPOINTER = "0b11111111111110" ;
    defparam FifoMacro_3_0.AEPOINTER1 = "0b00000000000000" ;
    defparam FifoMacro_3_0.AEPOINTER = "0b11111111111110" ;
    defparam FifoMacro_3_0.ASYNC_RESET_RELEASE = "ASYNC" ;
    defparam FifoMacro_3_0.GSR = "DISABLED" ;
    defparam FifoMacro_3_0.RESETMODE = "ASYNC" ;
    defparam FifoMacro_3_0.REGMODE = "OUTREG" ;
    defparam FifoMacro_3_0.CSDECODE_R = "0b11" ;
    defparam FifoMacro_3_0.CSDECODE_W = "0b11" ;
    defparam FifoMacro_3_0.DATA_WIDTH_R = 2 ;
    defparam FifoMacro_3_0.DATA_WIDTH_W = 2 ;
    FIFO8KB FifoMacro_3_0 (.DI0(scuba_vlo), .DI1(scuba_vlo), .DI2(Data[6]), 
        .DI3(scuba_vlo), .DI4(scuba_vlo), .DI5(Data[7]), .DI6(scuba_vlo), 
        .DI7(scuba_vlo), .DI8(scuba_vlo), .DI9(scuba_vlo), .DI10(scuba_vlo), 
        .DI11(Data[6]), .DI12(scuba_vlo), .DI13(scuba_vlo), .DI14(scuba_vlo), 
        .DI15(scuba_vlo), .DI16(scuba_vlo), .DI17(scuba_vlo), .CSW0(scuba_vhi), 
        .CSW1(scuba_vhi), .CSR0(RdEn), .CSR1(scuba_vhi), .FULLI(Full_int), 
        .EMPTYI(Empty_int), .WE(WrEn), .RE(scuba_vhi), .ORE(scuba_vhi), 
        .CLKW(WrClock), .CLKR(RdClock), .RST(Reset), .RPRST(RPReset), .DO0(Q[6]), 
        .DO1(Q[7]), .DO2(), .DO3(), .DO4(), .DO5(), .DO6(), .DO7(), .DO8(), 
        .DO9(), .DO10(), .DO11(), .DO12(), .DO13(), .DO14(), .DO15(), .DO16(), 
        .DO17(), .EF(), .AEF(), .AFF(), .FF());

    assign Empty = Empty_int;
    assign Full = Full_int;


    // exemplar begin
    // exemplar end

endmodule

Development Environment

Lattice Diamond 3.0.0.97

Active-HDL version 9.2

Target Device: LCMXO2-1200ZE-1TG144C

"Module not found" <=> FifoMacro_0_3 module code is missing. — Qiu, Feb 26 '14 at 12:57
Thanks for your comment. I think FifoMacro_0_3 is automatically generated module.I'm not sure where its RTL source code is. How can I find it? — yufit_in_Japan, Feb 26 '14 at 13:09
It might be a compiling order issue. Try instantiating `FifoMacro_*` before their `defparam`s. — Greg, Feb 26 '14 at 18:26
@Greg Thanks for your advice. I tried your suggestion. Unfortunately the same error occurred. — yufit_in_Japan, Feb 27 '14 at 13:10
@yufit_in_Japan, make sure `FIFO8KB` is being included in the compile and the correct parameters exist within it. — Greg, Feb 28 '14 at 17:18
Isn't this part of the standard libraries of Lattice? Are you sure you have compiled the libraries and your references to them are correct? This is a common problem when you first start with a new family or tools set. I am not familiar with Lattice, but I am sure you need to re-compile the libraries before you can use those in your simulation. — FarhadA, Mar 02 '14 at 20:09

score 2 · Accepted Answer · answered Mar 20 '14 at 05:57

2

Add these lines to your top level test bench:

GSR GSR_INST (.GSR (<global reset sig>));
PUR PUR_INST (.PUR (<powerup reset sig>));

See this Lattice FPGA How To document: How to Use the Global Set/Reset (GSR) Signal

answered Mar 20 '14 at 05:57

trayres

522
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RTL simulation of FIFO module by Active HDL (on Lattice Diamond)

1 Answers1