System verilog: Passing parameters to package

Question

I have to update few enumerated data types which are declared inside a package and mine is a special scenario where the size of my enum data type will vary with a parameter value. I have to make that parameter value somehow visible to the package.

I am aware that packages are not the components that can be instantiated. Hence I cannot pass the parameters directly.

Could anyone help me in getting my requirement done with help of some tweaks.

PS: The requirement is related to TB

Where do you want to change the parameters from? Do you want to import the package multiple times with different parameter values? — nguthrie, Feb 16 '14 at 02:06
It would really help to show us what you need to do with the enumeration if it could be parametrized. And by size, do you mean width? Why does that matter? enums are just mappings between labels and values where the value normally does not matter. — dave_59, Feb 16 '14 at 04:33
The package will be imported multiple times in various files. In a single run, a parameter can take a random value and accordingly the width of the enumerated data type which is defined in the package has to vary. — user3314064, Feb 16 '14 at 18:01
possible duplicate of [Handling parameterization in SystemVerilog packages](http://stackoverflow.com/questions/3895246/handling-parameterization-in-systemverilog-packages) — nguthrie, Feb 20 '14 at 22:22

score 3 · Answer 1 · answered Feb 16 '14 at 12:03

What we usually do for types of lengths that have to be parameterized is use defines instead of package parameters:

package some_package_pkg;
  `ifndef MAX_DATA_WIDTH
  `define MAX_DATA_WIDTH 32

  typedef [`MAX_DATA_WIDTH-1:0] bit some_type;
  ...
endpackage

By default, MAX_DATA_WIDTH is 32, but if we need a bigger width, we just pass the define from the command line. For Incisive it is something like:

irun -D MAX_DATA_WIDTH=64 some_package_pkg.sv

If you want to retrofit an existing package that uses a parameter you could do:

package some_param_package_pkg;
   parameter P_MAX_DATA_WIDTH = `MAX_DATA_WIDTH; // just add this line

   typedef [P_MAX_DATA_WIDTH-1:0] bit some_type; // all declaration are unchanged
endpackage

Tudor, Is "irun -D" simulation command? I am using questa. So is it equivalent to vsim ? — user3314064, Feb 16 '14 at 18:04
If you use Questa, then you have to specify the define when compiling: vlog +define+MAX_DATA_WIDTH=32 some_package_pkg.sv — Tudor Timi, Feb 17 '14 at 09:22

System verilog: Passing parameters to package

1 Answers1