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I'd like to patch gcc's sparc machine description so that the destination register of a FPU sqareroot operation fsqrts is stored into memory after each fsqrts.

like this:

fsqrts %f2,%f4
st %f4, -4[%fp]  <= add this after every fsqrts where -4[%fp] is
                            a slot allocated on the stack for each fsqrts insn

The sparc.md portion that defines the fsqrts pattern is:

(define_insn "sqrtsf2"
 [(set (match_operand:SF 0 "register_operand" "=f")
       (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
 "TARGET_FPU"
 "fsqrts\t%1, %0"
 [(set_attr "type" "fpsqrts")])

i thought I could add the "st %f4, -4[%fp]" there. But now my question:

  • Where/when/how can I allocate the stackframe slot to save the destination fpu reg in (the offset to %fp).

I'm not that familiar with rtl representation and the stages of compilation. So any help would be apreciated.

Maybe another architecture has a similar construct already that I could study and use for my purpose. If somebody can point me to such machine description part ...

unwind
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eiseled
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  • I managed to patch the .md description to issue the extra store, however now I was wondering about how to avoid beeing scheduled into a delay slot. Posted the patched .md at (with the scheduleing question): http://stackoverflow.com/questions/2236424/how-to-avoid-insn-beeing-scheduled-into-a-delay-slot – eiseled Feb 10 '10 at 11:36
  • Whatever you are trying to achieve, wouldn't the same thing be easier with some clever re#defining the appropriate C-level functions? – edgar.holleis Feb 20 '10 at 17:44

1 Answers1

2

Again, that's a question for gcc@gcc.gnu.org

F'x
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