Warnings in my code

Question

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.NUMERIC_STD.ALL; 
entity fir_123 is 
port(   Clk : in std_logic; --clock signal              
    Xin : in signed(7 downto 0); --input signal                
    Yout : out signed(15 downto 0)  --filter output             
    );                 
    end fir_123; 
architecture Behavioral of fir_123 is  
component DFF is 
port( 
Q : out signed(15 downto 0);      --output connected to the adder
Clk :in std_logic;      -- Clock input  

  D :in  signed(15 downto 0)      -- Data input from the MCM block.
 );   
end component;
signal H0,H1,H2,H3 : signed(7 downto 0) := (others => '0');  
signal MCM0,MCM1,MCM2,MCM3,add_out1,add_out2,add_out3 : signed(15 downto 0) := (others        => '0'); 
signal Q1,Q2,Q3 : signed(15 downto 0) := (others => '0');
begin  
--filter coefficient initializations.
--H = [-2 -1 3 4].
H0 <= to_signed(-2,8);  
H1 <= to_signed(-1,8);                    
H2 <= to_signed(3,8);                           
H3 <= to_signed(4,8); 
--Multiple constant multiplications.
MCM3 <= H3*Xin;                         
MCM2 <= H2*Xin;        
MCM1 <= H1*Xin;                      
MCM0 <= H0*Xin;  
--adders
add_out1 <= Q1 + MCM2;                            
add_out2 <= Q2 + MCM1;                          
add_out3 <= Q3 + MCM0;
--flipflops(for introducing a delay).
dff1 : DFF port map(Q1,Clk,MCM3);                                
dff2 : DFF port map(Q2,Clk,add_out1);                                         
dff3 : DFF port map(Q3,Clk,add_out2);
--an output produced at every positive edge of clock cycle.
process(Clk)                                          
begin 
if(rising_edge(Clk)) then  
Yout <= add_out3;  
end if;
end process;
end Behavioral; 
library IEEE;                                                     
use IEEE.STD_LOGIC_1164.ALL;                                     
use IEEE.NUMERIC_STD.ALL;
entity dff is                                                      
port(`
Q : out signed(15 downto 0);      --output connected to the adder                           
  Clk :in std_logic;      -- Clock input                                 
  D :in  signed(15 downto 0)      -- Data input from the MCM block. 
);  
end dff;
architecture Behavioral of dff is                       
signal qt : signed(15 downto 0) := (others => '0'); 
begin                          

Q <= qt;                              

process(Clk)                                   
begin 
if ( rising_edge(Clk) ) then 
qt <= D; 
end if;  
end process; 
end Behavioral;

When I run this code it compiles successfully error free syntax but I get several warning and because of that I am not getting desired result. I get Xin, Clkin & Yout undefined in simulation result. I tried in different ways but still I haven't resolved these warnings:

1) WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.

2) WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.

3) WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.

4) WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during

Please paste code that is indented pleasantly, and compiles (eg. there's a backtick on one line of code!) Until that happens, it's unlikely people will spend the time trying to understand your problem. You have to make life as easy as possible for us! — Martin Thompson, Feb 05 '14 at 11:53
The main question is a duplicate of http://stackoverflow.com/questions/12171815/vhdl-synthesis-warning-ff-latch-has-a-constant-value-of-0/12172569 - have a look at the answer there. — sonicwave, Feb 05 '14 at 12:07
The warnings are probably to be expected : given your filter coefficient values, many bits in the products will always be 0 ond can be optimized out in synthesis. If there's anything wrong in this code, you haven't shown us what... as i said in the duplicate, show the testbench. (H0 to H3 could be constants instead of signals, but again that isn't the problem) — , Feb 05 '14 at 12:21

score 0 · Answer 1 · answered Feb 14 '14 at 17:24

There seems to be no problem with the code. The only thing that I thought could go wrong is the fact that the fir module doesn't have any reset. The code for fir is as follows:

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.NUMERIC_STD.ALL;

entity fir_123 is 
port(   Clk : in std_logic; --clock signal
        reset: in std_logic;     
    Xin : in signed(7 downto 0); --input signal                
    Yout : out signed(15 downto 0)  --filter output          
    );                 
end fir_123;


architecture Behavioral of fir_123 is  
component DFF is 
port( 
  Q : out signed(15 downto 0);      --output connected to the adder
  Clk :in std_logic;      -- Clock input  
  reset: in std_logic;
  D :in  signed(15 downto 0)      -- Data input from the MCM block.
 );   
end component;

signal H0,H1,H2,H3 : signed(7 downto 0) := (others => '0');  
signal MCM0,MCM1,MCM2,MCM3,add_out1,add_out2,add_out3 : signed(15 downto 0) := (others => '0'); 
signal Q1,Q2,Q3 : signed(15 downto 0) := (others => '0');

signal yout_int : signed(15 downto 0);

begin  
--filter coefficient initializations.
--H = [-2 -1 3 4].
H0 <= to_signed(-2,8);  
H1 <= to_signed(-1,8);                    
H2 <= to_signed(3,8);                           
H3 <= to_signed(4,8); 
--Multiple constant multiplications.
MCM3 <= H3*Xin;                         
MCM2 <= H2*Xin;        
MCM1 <= H1*Xin;                      
MCM0 <= H0*Xin;  
--adders
add_out1 <= Q1 + MCM2;                            
add_out2 <= Q2 + MCM1;                          
add_out3 <= Q3 + MCM0;
--flipflops(for introducing a delay).
dff1 : DFF port map(Q1,Clk,reset,MCM3);                                
dff2 : DFF port map(Q2,Clk,reset,add_out1);                                         
dff3 : DFF port map(Q3,Clk,reset,add_out2);
--an output produced at every positive edge of clock cycle.

registered_yout: process                                          
begin
  wait until rising_edge(clk);
  if (reset = '1') then
    yout_int <= (others => '0');
  else
    yout_int <= add_out3;  
  end if;
end process;

Yout <= yout_int;

end Behavioral;

I also added in reset for dff and the changed file looks like this:

library IEEE;                                                     
use IEEE.STD_LOGIC_1164.ALL;                                     
use IEEE.NUMERIC_STD.ALL;

entity dff is                                                      
  port(
    Q : out signed(15 downto 0);      --output connected to the adder                           
    Clk :in std_logic;      -- Clock input
    reset: in std_logic;                                 
    D :in  signed(15 downto 0)      -- Data input from the MCM block. 
);  
end dff;

architecture Behavioral of dff is                       
signal qt : signed(15 downto 0) := (others => '0'); 
begin                          

Q <= qt;                              

registered_qt : process                                  
begin
  wait until rising_edge(clk);
  if (reset = '1') then
    qt <= (others => '0');
  else 
    qt <= D;
  end if;
end process;

end Behavioral;

The testbench that I used is as follows:

library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity tb is
end entity tb;

architecture test_bench of tb is

component fir_123 is 
port(   Clk   : in  std_logic;
        reset : in std_logic;          
        Xin   : in  signed(7 downto 0);                
        Yout  : out signed(15 downto 0)            
    );                 
end component fir_123;

constant clk_per : time := 8 ns;

signal clk: std_logic;
signal reset: std_logic;

signal Xin  : signed(7 downto 0);
signal Yout : signed(15 downto 0);

begin

dft : component fir_123
port map (
    Clk     => clk,
    reset   => reset,
    Xin     => Xin,
    Yout    => Yout
);

Clk_generate : process --Process to generate the clk
begin
    clk <= '0';
    wait for clk_per/2;
    clk <= '1';
    wait for clk_per/2;
end process;

Rst_generate : process --Process to generate the reset in the beginning
begin
    reset <= '1';
    wait until rising_edge(clk);
    reset <= '0';
    wait;
end process;


Test: process

begin
  Xin <= (others => '0');
  wait until rising_edge(clk);
  Xin <= (others => '1');
  wait until rising_edge(clk);
  Xin <= (others => '0');

  wait for clk_per*10;
  report "testbench finished" severity failure;
end process test;

end architecture test_bench;

I have checked the waveforms in a simulator and they all seem to be defined after the reset has been deasserted. The fact that Xin and Clk is undefined shows that there is something wrong with the testbench.

Warnings in my code

1 Answers1