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When writing compilers for standard computers, one can target an existing intermediate representation (like LLVM IR) and not have to worry about tricky architectural differences between systems. Does something like this exist for FPGAs?

Dan
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    One intermediary level is the purely structural RTL which can be represented e.g. as an EDIF netlist (but often this already contains architecture dependant blocks). Or do you refer to an earlier representation in the dataflow, i.e. still containing some behavioral aspects? To some extent the synthesizable subsets of Verilog/VHDL actually take this role in many toolchains. – mbschenkel Feb 04 '14 at 16:10
  • I was looking for something that is not behavioral. – Dan Feb 05 '14 at 01:16
  • I'm intrigued to know why you would want to do this...? – Martin Thompson Feb 06 '14 at 11:53
  • @MartinThompson To develop an experimental HDL. – Dan Feb 06 '14 at 13:33
  • @Dan - ahh, fun! Answer updated... – Martin Thompson Feb 07 '14 at 09:52

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Not really. The synthesis tools are very architecture-aware already, so the output netlist is already tailored to the target device.

The closest you could come would be to use ASIC tools to target a simple library of gates and flipflop. That would produce a "lowest-common denominator" netlist (although it wouldn't then be efficient to re-target to an FPGA as getting back from that representation to "it was an adder, so I can use the carry-chain" is non-trivial.

Update - I see you want to develop an experimental HDL...

I would suggest that if you want to go from your experimental HDL to a bitstream that you just output VHDL or Verilog and then run the traditional tools. My feeling is that you really don't want to be responsible for mapping (eg) adders to LUTs+carry chains, as it'll take you years to be as good as the current tools.

If you haven't already, take a look at how MyHDL does a similar thing.

Martin Thompson
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