BCD to 7 segment Decoder

Question

I just started VHDL coding, and right now have to code a BCD to 7 segment decoder. I am doing a Behavioral design(it's required) but right now I am having trouble on how to code the display.

I know how to code this decoder with just one input and one output, however we have a second output called DIGEN_L which is used as our display. It is an active low bus output that enables each digit of the 7-segment display on our board.

He told us to just program it to '01110 so the fourth digit is always on and the other three are off.

I do not know how to code DIGEN_L into my code, and do not know what the above statement actually means (code wise). Can anyone help? If any clarification is needed on this question, comment and I will edit.

Here is my code:

library IEEE;
ise IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity decoder is
    port( BCD: in STD_LOGIC_VECTOR (3 downto 0);
        ( SEGS_L: out STD_LOGIC_VECTOR(5 downto 0);
        ( DIGEN_L: out STD_LOGIC_VECTOR(3 downto 0));
end decoder;

architecture decoder_arc of decoder is
    begin
       process(BCD)
          begin
         DIGEN_L <= "0111";
         case BCD is
            when "0000"=> SEGS_L <="1111110";  -- '0'
            when "0001"=> SEGS_L <="0110000";  -- '1'
            when "0010"=> SEGS_L <="1101101";  -- '2'
                when "0011"=> SEGS_L <="1111001";  -- '3'
                when "0100"=> SEGS_L <="0110011";  -- '4' 
            when "0101"=> SEGS_L <="1011011";  -- '5'
            when "0110"=> SEGS_L <="1011111";  -- '6'
            when "0111"=> SEGS_L <="1110000";  -- '7'
            when "1000"=> SEGS_L <="1111111";  -- '8'
            when "1001"=> SEGS_L <="1111011";  -- '9'
            when others=> SEGS_L <="-";
             end case;
       end process;
end decoder_arc;

Please note that when others=> SEGS_L <="-"; is not synthesizable. Either make a real assignment (e.g. all lamps on, all lamps off) inside the case statement or make a default assignment at the top of the process: decode_bcd_proc: process (BCD) begin SEGS_L <= (others => '0'); case BCD is ... end process decode_bcd_proc; — FRob, Feb 03 '14 at 19:25

score 2 · Accepted Answer · answered Feb 02 '14 at 18:26

So basically, you have a 4 digit display with each digit being a 7-segment display.

Now, you have four low-active digit enable DIGEN_L for each digit. (Btw, why did your vector have five bits?)

The idea here is that you code your BCD to 7-seg decoder as you would normally do. So we have our entity

entity bcd2sevseg {

    BCD       : in std_logic_vector(3 downto 0);
    SEVEN_SEG : out std_logic_vector(6 downto 0);
    DIGEN_L   : out std_logic_vector(3 downto 0)

};

Now, you said how to code the actual decoder, so BCD and SEVEN_SEG should be clear. Your professor asked that you supply a static value to DIGEN_L. So just go ahead and do that:

DIGEN_L <= "0111";

The idea here is that all 7-segment displays share the same signals for the individual segments (SEVEN_SIG if you will). However, all drains for the LEDs are connected to individual lines, DIGEN_L (or progrably a transistor controlled by DIGEN_L). So if you switch DIGEN_L rapidly while supplying a different digit on each switch, you will see that all four digits display their respective number, because of persistence of vision.

However, in your example, you will start out with just having one digit and a future assignment will be to display two or more digits, where you will learn how to multiplex and possibly concern yourself with pulse-width modulation for dimming individual digits.

thanks for the thorough explanation, it definitely helped!! One more question though, where would I place DIGEN_L <= "0111"; in my code? I edited it above to see where I thought it would be placed. — AOE, Feb 03 '14 at 19:16
Placement of DIGEN_L is fine inside the process. However, signal assignments can also be made parallel to processes (b/c they are parallel statements as well as sequential statements). Since there is no dependency on BCD, you might as well place it outside the process - but within the architecture. — FRob, Feb 03 '14 at 19:23

score 1 · Answer 2 · answered Dec 03 '15 at 23:40

LIBRARY IEEE;   
USE IEEE.STD_LOGIC_1164.ALL;    
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
USE IEEE.STD_LOGIC_ARITH.ALL;


ENTITY seven_segment IS

    port(BCD: in std_logic_vector(3 downto 0);
        clk,reset: in std_logic;
        sseg: out std_logic_vector(6 downto 0));

END seven_segment;

ARCHITECTURE SSD OF seven_segment IS

signal temp: unsigned(6 downto 0);

BEGIN

process(clk,temp)

BEGIN
if reset = '1' OR BCD > "1001" then
    temp <= (others => '0');

    elsif rising_edge(clk) then
                              -- abcdefg
elsif BCD = "0000" then temp <= "1111110"; -- 0
elsif BCD = "0001" then temp <= "0110000"; -- 1
elsif BCD = "0010" then temp <= "1101101"; -- 2
elsif BCD = "0011" then temp <= "1111001"; -- 3
elsif BCD = "0100" then temp <= "0110011"; -- 4
elsif BCD = "0101" then temp <= "1011011"; -- 5
elsif BCD = "0110" then temp <= "1011111"; -- 6
elsif BCD = "0111" then temp <= "1110000"; -- 7
elsif BCD = "1000" then temp <= "1111111"; -- 8
elsif BCD = "1001" then temp <= "1111011"; -- 9

end if;

sseg <= std_logic_vector(temp);

END process;
END SSD;

BCD to 7 segment Decoder

2 Answers2