Why is this verilog relational statement returning true?

Question

I have a 9 bit signed wire called sin_hall2.

This statement returns true. sin_hall2[8:0]>9'd1.

When I look at my simulation, sin_hall2=-169. I am assuming it is the way verilog deals with comparing negative numbers, but what am I doing wrong. I receive the same result when I do sin_hall2[8:0]>9'sh001.

Please show all the relevant code including the definition of `sin_hall2` — Morgan, Jan 24 '14 at 18:56

score 8 · Answer 1 · answered Jan 24 '14 at 19:07

Signed numbers use the twos-complement format. that is if interpreted as unsigned they will appear as large numbers, the second half of the unsigned number range.

If any section of a comparison is unsigned then the comparison is unsigned. Selecting bit widths, even if the whole range, is unsigned

reg signed [8:0] sin_hall2;

initial begin
  sin_hall2 = -9'd169 ;
  $display( "Comparison unsigned : %b ", sin_hall2 > 9'd1 );
  $display( "Comparison cast     : %b ", sin_hall2 > $signed(9'd1) );
  $display( "Comparison signed   : %b ", sin_hall2 > 9'sd1 );
  $display( "Comparison signed [8:0]: %b ", sin_hall2[8:0] > 9'sd1 );
end

Returns:

# Comparison unsigned : 1 
# Comparison cast     : 0 
# Comparison signed   : 0
# Comparison signed [8:0]: 1

Example on EDA Playground.

Why is this verilog relational statement returning true?

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