In the X86 architecture how does a processor know that a page is not mapped in main memory but is in backing store, is their a flag in the page table entry that indicates that or is it only after the translation into physical address that the processor realizes the location of the Frame? In my understanding when the 'P' flag in the Page structure entry is set it indicates that a valid mapping for the logical address does not exist and a Page fault follows, in case when the mapping is present but the page is in backing store than also Page fault occurs and the page is swapped into memory and the page table entry modified.
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I think you are referring to a HARD page fault VS a SOFT page fault. A hard page fault will be fired if:
- P(resent) flag is not set / no entry in page table exists
- User mode code is writing a read only memory
- User mode code is accessing kernel memory
- Page entry reserve bits are corrupted.
A soft page fault will fire if the page is present but is else ware in memory (maybe on a different working set or leaving the working set)
http://blogs.technet.com/b/askperf/archive/2008/06/10/the-basics-of-page-faults.aspx http://en.wikipedia.org/wiki/Page_fault (minor vs major)
hope this help :)

0xGiddi
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Thanks for your response, I am talking about major page fault(page in backing store) but the specific question is that how does the hardware(processor) differentiate between a major page fault and a hard page fault, how does ISR gets to differentiate between them? The hardware MMU must have left a hint in some register before raising an fault which would help ISR make the distinction enabling it to execute the corresponding steps. – S. Aditya Jan 20 '14 at 17:11
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1The CPU dose not know that it's a soft page fault since the CPU is not the one that manages paging and memory management. It is up to the ISR to determine if it's a soft or hard page fault. The OS can see that address that caused that fault in register CR2 and check if it is virtually loaded and was moved out of memory – 0xGiddi Jan 21 '14 at 15:27
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A trick that may be done is keeping a PTE with the present flag 0 and the PBA pointing to the location of the page in a pagefile. When a page fault fires you can load the data from the page file that corresponds to the PBA and and switch out the entry – 0xGiddi Jan 21 '14 at 15:49