vhdl-fsm with timer- clock cycle delay

Question

i have to write in vhdl an FSM with timer.

I think that,there is no need you to get tired of understanding what my circuit will do.

I just wanted to help me with this: Every change from a state to another state, there is one (or more) clock cycle delay. The question is, how can i avoid it?

my vhdl code:

library IEEE;
   use IEEE.STD_LOGIC_1164.ALL;
   use IEEE.STD_LOGIC_unsigned.ALL;

entity fsm_timers is
port( x: in bit; 
      clk, rst: in std_logic;
        y: out bit);
end fsm_timers;

architecture Behavioral of fsm_timers is
constant T1: std_logic_vector(7 downto 0) :="00000011";                                                       
constant T2: std_logic_vector(7 downto 0) :="00000111";               
signal t: std_logic_vector(7 downto 0) := (others=>'0');
signal rst_cnt: std_logic :='0';

Type state is (A,B,C);
signal pr_state, nx_state : state := A;

component counter is
 port(reset,clock, inner_rst:in std_logic;
      cnt:out std_logic_vector(7 downto 0));
 end component;
begin
U_sum_counter: counter port map(
        reset => rst,
        inner_rst => rst_cnt,
        clock => clk,
        cnt => t);

process(clk,rst)
begin
    if (rst='1') then
        pr_state<= A;
    elsif (rising_edge(clk)) then
       pr_state<=nx_state;
    end if;

end process;

process(x,t,pr_state)
begin
    case pr_state is
        when A =>
            y<='0';
            rst_cnt<='1';
            if (x='1') then             
                nx_state<= B;
            else 
                nx_state<= A;
            end if;
        when B =>
            y<='0';
          rst_cnt<='0';
            if (x='0' and t=(T1-1)) then
                nx_state<= C;
            end if;
            if ((x='0' and t<(T1-1)) or (x/='0' and t<(T2-1))) then
                nx_state<= B;                   
            end if;
            if (t=(T2-1)) then
                nx_state<= A;
            end if;
        when C =>
            y<='1';
          rst_cnt<='0';
            if (t=(T2-1)) then
                nx_state<= A;
            else
                nx_state<= C;
            end if;
    end case;
end process;
end Behavioral;

Thank you in advance

score 1 · Answer 1 · answered Feb 12 '14 at 22:31

I think you can't avoid at least a single clock delay. The reason is that you have to remember your current state. For saving the state you have to use a register, which will cause the delay. Otherwise you can avoid this by using an asynchronous state machine, but then you will have to be careful about your input.

A usual Moore's state machine has:

           \/-------------|

input --> transition logic --> state memory --> output logic --> output

                    ^-clk ^-rst ^-enable

This structure can be nicely expressed by 3 processes. For trying to reduce the latency, you can connect the output logic directly to the transition logic, but you might need a register after that anyway.

For details see this page i googled, it is pretty detailed.

vhdl-fsm with timer- clock cycle delay

1 Answers1