4 bit U/D counter in VHDL

Question

I'm trying to code in VHDL a 4 bit counter that counts from "0000" to "1111" or from "1111" to "0000" depending on the value of my UD variable (if UD='1' it should count down and if it's ='0' up). There is also a signal RCO_L that gets value='0' when my counter reaches one of the sides of the counter (0 or 15). Lastly there's a ENP_L signal that inhibits my counter when it's set to 1.

I'm finding it hard to code since I'm kind of new to VHDL and I'm getting lots of errors. If anyone could help me I'd really appreciate it.

This is what I've done so far:

*entity contador is
    Port ( A : in  STD_LOGIC_VECTOR(3 downto 0);
           CLK : in  STD_LOGIC;
           LOAD_L : in  STD_LOGIC;
           UD : in  STD_LOGIC;
           ENP_L : in  STD_LOGIC;
              Q : out  STD_LOGIC (3 downto 0);
           RCO_L : out  STD_LOGIC);
end contador;
architecture Behavioral_contador of contador is
signal contador : STD_LOGIC_VECTOR(3 downto 0);
begin
process (CLK,UD,LOAD_L,ENP_L)
    begin
    if (CLK'event AND LOAD_L='0') then
        Q <= A;
    elsif (CLK'event AND LOAD_L='1') then
        if (UD='0') then
            contador <= contador + 1;
        elsif (UD='1') then
            contador <= contador - 1;
        end if;
        if (contador="0000" and ENP_L='0') then
            RCO_L='0';
            if (UD='0') then
                contador="0001";
            elsif (UD='1') then
                contador="1111";
            end if;
        else
        RCO='1';
        end if;
    end if;
end process;
Q <= contador;
end Behavioral_contador;*

PD if it helps this is the error console results:

*ERROR:HDLCompiler:535 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 40: Index constraint prefix std_logic should be an array type
ERROR:HDLCompiler:854 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 34: Unit <contador> ignored due to previous errors.
ERROR:HDLCompiler:374 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 44: Entity <contador> is not yet compiled.
ERROR:HDLCompiler:69 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 46: <std_logic_vector> is not declared.
ERROR:HDLCompiler:69 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 53: <q> is not declared.
ERROR:HDLCompiler:69 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 56: <contador> is not declared.
ERROR:HDLCompiler:69 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 58: <contador> is not declared.
ERROR:HDLCompiler:69 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 57: <ud> is not declared.
ERROR:HDLCompiler:69 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 55: <ud> is not declared.
ERROR:HDLCompiler:806 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 61: Syntax error near "=".
ERROR:HDLCompiler:806 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 63: Syntax error near "=".
ERROR:HDLCompiler:837 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 63: Type  void does not match with a string literal
ERROR:HDLCompiler:806 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 65: Syntax error near "=".
ERROR:HDLCompiler:837 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 65: Type  void does not match with a string literal
ERROR:HDLCompiler:69 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 64: <ud> is not declared.
ERROR:HDLCompiler:69 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 62: <ud> is not declared.
ERROR:HDLCompiler:806 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 68: Syntax error near "=".
ERROR:HDLCompiler:69 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 60: <contador> is not declared.
ERROR:HDLCompiler:69 - "/home/edig/Escritorio/vhdl/contador.vhd" Line 54: <clk> is not declared.*

score 1 · Answer 1 · answered Dec 16 '13 at 21:14

First, your count variable should be of type unsigned not std_logic_vector. If you want a vector to represent a number, choose the right type.

Second, just have a single clk'event line. In fact the idiom these days is to use the rising_edge(clk) function instead. You don't need all those signals in your sensitivity list, just the clock.

Then have all your control logic inside the if rising_edge(clk) then.

Once you've fixed all the syntax errors (use the compiler, or get an editor like Sigasi's, then build a testbench which will create the clock and other input signals so you can see if it is working. For extra credit, make the testbench actually check that the outputs do what you want, rather than staring at waveforms yourself - that get's tedious very quickly!

Also, advice for the future - if you're asking questions here, please post code that is

indented properly (again, use Sigasi, it's free for small code and just does the job)
free of syntax errors.

Sloppily asked questions are unlikely to get much in the way of answers, sorry!

score 0 · Answer 2 · edited May 23 '17 at 12:19

0

Most of them are syntax errors. For example Q should be std_logic_vector. Also when you need to write something at output, you mention like this: output <= input instead of RCO_L='0'; . Signal contador is of std_logic_vector and you can not increment/decrement 1 in std_logic_vector in this way. First you have to convert them to unsigned values, just mentioned here

edited May 23 '17 at 12:19

Community

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answered Dec 16 '13 at 19:26

Digeek

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For more information check [Xilinx XST](http://www.xilinx.com/itp/xilinx10/books/docs/xst/xst.pdf) manual. – Digeek Dec 17 '13 at 15:11

4 bit U/D counter in VHDL

2 Answers2