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I have implemented a HDMI Transmitter and receiver on a Atlys Spartan 6 board. Its working properly. I am using 1080p @ 60Hz. The board takes a one pixel, decodes it, encode it back and send it to the monitor.

Now i need to identify the start of a new frame. Because i want to draw a square on the middle of the screen (using the FPGA). I thought when both HSYNC and VSYNC are '1' that implies a start of a new frame. But it seems that is not the case.

Can anyone tell me abot how to identify the start of new HDMI frame?

Thank you!

user2389323
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    Where HSYNC and VSYNC both go to '1' should in fact be the start of the new frame. Are you looking for the positive edge on both of those signals? – Russell Nov 25 '13 at 20:21
  • Thanks for your reply.... always @ (posedge pclk) begin if(h_sync & v_sync) begin start = 1'b1; end This is part of the code. pclk is the pixel clk. – user2389323 Nov 25 '13 at 20:40
  • read this post about looking for edges. The way you described in your comment is not sufficient. You need to register the previous value of the signal, the current value of the signal, and look for the condition when the previous value = 0 and the current value = 1. http://stackoverflow.com/questions/8413661/proper-way-for-signal-edge-detection-in-verilog. – Russell Nov 25 '13 at 21:54
  • The idea behind my coding part is, it will start counting frames from zero, soon after it detects(h_sync & v_sync). Those two are wires cumming out from a output register of a decode module. After the first time i set variable 'start' to '1', i start counting. So why isnt it correct? – user2389323 Nov 26 '13 at 02:16

1 Answers1

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The start of a new frame is after VSYNC has changed to '1' and later (or at the same time, it depends on your data source) HSYNC has also changed to '1'.

You need to detect edges. In VHDL, a process like this:

process(clk)
   variable last_hsync, last_vsync, got_vsync : std_logic;
begin
   if rising_edge(clk) then
       if vsync = '1' and last_vsync = '0' then
           got_vsync := '1';
       end if;
       if got_vsync and hsync = '1' and last_hsync = '0' then
           first_pixel <= '1';
       end if;
       last_vsync := vsync;
       last_hsync := hsync;
    end if;
end process;

That may flag a false start of frame if you come up mid-frame - you may need some extra state to manage those cases, if it matters, but that's system dependent.

Martin Thompson
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