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Ive made a simple ticker module that produces a rick every time the counter reaches 163. Here is the code for it:

    module baud_gen(
    input clock,
    input reset,
    output tick
    );

reg [7:0] count;

always @ (posedge clock)
begin
    if(reset || (count == 163))
        count <= 0;
    else
        count <= count + 1;
end

assign tick = (count == 163) ? 1:0;

endmodule

It works as it should, in simulation when the counter reaches 163, tick is assigned high and otherwise its 0.

Now I instantiated this into my UART receiver. Here is the code snippet:

module receiver(
    input clock,
    input reset,
    input s_tick,
    input rx,
    output reg done,
    output [7:0] word_out
    );

    localparam [1:0]
            idle = 00,
            start = 01,
            data = 10,
            stop = 11;

    baud_gen ticker (.clock(clock), .reset(reset), .tick(s_tick));
   .
   .
   .
   .

Now when I run the simulation for the receiver module. The ticker does not work correctly. Here instead of producing a 1 at count==163 it produces a x.

Here is the simulation of it when it has been instantiated into receiver module:

enter image description here

I cannot figure out why this change in behavior. Thank you for looking

StuckInPhDNoMore
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1 Answers1

4

Best guess there is a second driver on tick somewhere in the design. Easy way to find out is to change the tick assignment in baud_gen to:

wire pre_buf_tick = (count == 163) ? 1:0;
assign tick = pre_buf_tick;

Probe both signals. Odds are pre_buf_tick will be 1 when tick is X.

The cause of the conflicting driver might be related to s_tick being listed as an input of the receiver when it should be an output.

Greg
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  • Thank you. ``s_tick`` is supposed to be an input to this module, and this tick is produced by the ``bau_gen``. I have to connect the output ``tick`` to the ``s_tick``. I'm new to instantiation. Can I not instantiate an output from one module to the input of another? – StuckInPhDNoMore Nov 22 '13 at 15:25
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    @FarazKhan no output from a submodule can not drive the input to the containing (instantiating) layer. inputs can only be driven from the level above, other wise they are not inputs. – Morgan Nov 22 '13 at 17:29
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    @FarazKhan , Morgan is 100% correct. I was about to write the same thing. If you need to merge the two, you can always create another wire, example `wire merge_tick = s_tick || tick;`. You could switch to `inout` with tri-state drivers but I would discourage it. Tri-states can easily have conflicting drivers if not implemented property and tend to be harder to debug. Some FPGAs tend to have limited tri-state support as well. – Greg Nov 22 '13 at 17:49