understanding communication delays in parallism

Question

I am reading through "Computer Architecture: A Quantative Approach, 5th ed" and am looking at an example from Chapter 5 on page 350. Attached is a scan of the example in question. I do not quite follow the logic of how they do things in this example.

My questions are, as follows:

1. Where is the 0.3ns cycle time coming from?
2. 200/0.3 is roughly 666 cycles, I follow this. However, when plugged back into the CPI equation, it makes no sense: 0.2% (0.002) x 666 is equal to 1.332 and not 1.2. What is going on here?
3. When they say that "the multiprocessor with all local references is 1.7/0.5 = 3.4 times faster", where are they getting that from? Meaning: I see nowhere in the given information stating that local communication is twice as fast...

Any help would be appreciated.

Answer 1

Where is the 0.3ns cycle time coming from?

That comes from the clock rate of 3.3 GHz. 1 / 3.3 GHz = 0.3ns.

200/0.3 is roughly 666 cycles, I follow this. However, when plugged back into the CPI equation, it makes no sense: 0.2% (0.002) x 666 is equal to 1.332 and not 1.2. What is going on here?

I think you're right. That looks like a misprint. That should be

CPI = 0.5 + 1.33 = 1.83

When they say that "the multiprocessor with all local references is 1.7/0.5 = 3.4 times faster", where are they getting that from? Meaning: I see nowhere in the given information stating that local communication is twice as fast...

They don't say anywhere that local communication is twice as fast. They're dividing the effective CPI that they calculated for the multiprocessor with 0.2% remote references by the base CPI of 0.5. This tells you how many times faster the multiprocessor with all local references is. (Of course it should be about 1.83/0.5 = 3.66 times faster.)