0

Suppose we have a simple processor, could be an embedded system, with one system bus, for the sake of the argument, a 32bit bus.

Now, if we have a couple of Peripherals, one named PER0 for example, attached to the bus, we can do two things:

  1. Allow it to have fixed-width access to the main bus, for example 8 bits, and that way PER0 will always communicate with the bus in 8bit packages. This we can call static-width access.

  2. Allow it to have options to choose how it will communicate with the bus in terms of size of data by using signals with which it tells the processor the mode of access it wants to use. For example, we create two signals, A1 and A0, between the processor and PER0, whose values will say:

    00 - wait
    01 - 8bit
    10 - 16bit
    11 - 32bit

    and so the processor will know whether to send 8bit data to its bus, or 32bit data, based on the values of A1, A0. This we can call dynamic-width access to the bus.

Question: In your experience, which of these two methods is preferred, and why? Also, in which cases should this be implemented? And finally, considering embedded systems, which method is more widely spread?

EDIT: I would like to expand on this topic, so I'm not asking for personal preferences, but for further information about these two methods, and their applications in computer systems. Therefore, I believe that this qualifies as a legitimate stackoverflow question.

Thanks!

Vidak
  • 1,083
  • 14
  • 29
  • modern processor busses use bytemasks or other controls to determine which lanes have new data for a write and for reads a length that indicates how big/wide the transfer should be. As to your question, this is an opinion question, so it really doesnt fit with stackoverflow. – old_timer Nov 06 '13 at 18:39
  • 1
    You always configure the address range for **PER0** in your CPU memory controller. If your peripheral has a mix of 32/16/8 bit registers, you must always access as 32bit and mask the un-driven bits. A memory device will always be symmetric (no mixing 8/16/32). You always statically configure it as the extra lines will cost money. You can add pull-ups/downs on a BOM if you want to make your software work on two different stuffings and *probe* the device to determine the width and then configure the memory controller. You question is highly dependent on the CPU architecture. – artless noise Nov 07 '13 at 15:19

1 Answers1

1

There are multiple considerations. Naturally, the dynamic-width would allow better utilization of bandwidth in case you have multiple sizes in your transactions. On the other hand, if you transfer some 8 bytes, and then the next 8, you double the overhead compared to the baseline (transferring the full block in one go, assuming you can cache it until it fully consumed). So basically you need to know how well you can tell in advance which chunks you're going to need.

There's an interesting paper about the possibility of using such a dynamic sized transactions between the CPU and the DRAM:

Adaptive granularity memory systems: a tradeoff between storage efficiency and throughput

There you can see the conflict since it's very hard to tell which transactions you'll need in the future and whether bringing only partial data may cause a degradation. They went to the effort of implementing a predictor to try and speculate that. Note that this is applicable to you only if you're dealing with coherent memory.

Leeor
  • 19,260
  • 5
  • 56
  • 87