Verilog disable Statement not Working but $finish works but it is not synthesizable?

Question

I want to design an counter which counts up to some number, lets say it is 3, for this I write a code that work well with "$finish" but not with "disable".

I want to use this counter for synthesis so I have to use "disable" statement .....

I have attached my both code- (1) With $finish that stops easily & accurately

// Code with $finish   
module counter(input wire  clk);

reg [23:0]N=24'b0000_0000_0000_0000_0000_0000;

always @ (posedge clk)
 begin 

  if (N == 24'b0000_0000_0000_0000_0000_0011)
   begin 
    $display("Inside If N=%d in Time=",N,$time);
    $finish;
   end
   else 
   begin 
    N <= N +1;    
    $display("Inside Else N=%d in Time=",N,$time);
   end 
  end

endmodule

(2) With disable that not stop at all..

// Code with disable that not stop    
module counter(input wire  clk);

reg [23:0]N=24'b0000_0000_0000_0000_0000_0000;

always @ (posedge clk)
 begin :close

  if (N == 24'b0000_0000_0000_0000_0000_0011)
   begin 
    $display("Inside If N=%d in Time=",N,$time);
    disable close; 
  end
  else 
  begin 
    N <= N +1;    
    $display("Inside Else N=%d in Time=",N,$time);
  end 
 end

endmodule

sir so according to you what is the change that I need to do......I mean can you briefly describe it by giving some code... — Shrikant Vaishnav, Oct 16 '13 at 18:53

Greg · Answer 1 · 2017-12-18T21:51:46.300

0

Put the $finish at the end of your test bench, not in your synthetically RTL.

$finish stops all running processes and ends the simulation. disable stops one process and its child processes. In your sample code, disable close terminates the code within the always block, it does not stop the clock. The next positive edge clock and the always block will try to run again.

See IEEE std 1800-2012 § 20.2 for the $finish statement and § 9.6.2 for the Disable statement

edited Dec 18 '17 at 21:51

answered Oct 16 '13 at 19:06

Greg

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Greg sir but in actual hardware how can I stop a clock that nothing but a clock of FPGA ......I mean as you describe that I have to disable top level module and not the design unit ... – Shrikant Vaishnav Oct 16 '13 at 19:14
Look at the clock generator module definition. There is usually a input port for enabling/disabling it. – Greg Oct 16 '13 at 19:20

Morgan · Answer 2 · 2013-10-17T06:40:12.590

toolic and Greg have both indicated to incorrect uses of $finish and disable, this is just to add to both of those points and show a possible solution, seperating test from synthesizable RTL.

module counter(input clk);

  reg [23:0] N = 24'b0;

  always @ (posedge clk) begin 
    if (N < 24'd3) begin 
      N <= N +1; 
      $display("Inside If N=%d in Time=",N,$time);
    end
    else begin 
      $display("Inside Else N=%d in Time=",N,$time);
    end 
  end
endmodule

To test it:

module test;

//Create clk
reg clk;
initial begin
  clk = 0 ;
  forever begin
    #5  clk =   ~clk;
  end
end

//instantiate DUT (Device Under Test)
counter counter_i0(
  .clk( clk )
);

// The test
//  Run for 6 clock cycles then end
initial begin
  repeat (6) begin
    @(posedge clk)
  end
  $finish;
end
endmodule

If you mean to stop at count 3, I would use decimal notation 24'd3 for the constant, as it gives clear intent.

also if using == to stop a counter a glitch could cause this to be missed and you have to wait for this to wrap arround. Or using a less than comparator means that the count target can be adjusted on the fly with out fear of skipping the exact value in == and having to wait a really long time for it to wrap around.

inputs are implicitly wires, no need to define them as such but you can if you want.

Verilog disable Statement not Working but $finish works but it is not synthesizable?

2 Answers2