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Is it synthesizable to use:

  • case statement within a case statement
  • case statement within an if statement
  • if statement within a case statement

I can compile it without any errors, but I'm still not sure if it would mess up the hardware structure and make it to complex.

Reason why I'm doing this:

I have a couple of states (state machine), and to make them go through all states I use case statements. But I also need to make some conditions (cases and ifs) within some of these states, some of them are quite big.

Martin Thompson
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user2849959
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    I would recommend that you're careful, otherwise you'll have a hard time trying to synthesize it. Long carry-chains of logic will have trouble at high clock rates. – Russell Oct 10 '13 at 21:03
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    Nesting if/case, case/if, or case/case is OK, and I assume the synthesis tool handles this like another way of describing conditional code, just like nesting if/if. However, remember that the tool has to make hardware of you description, so imagine the hardware you code. – Morten Zilmer Oct 11 '13 at 03:50
  • Not sure if I should bump this thread, but a thank you is a must. Thank you! Cheers – user2849959 Oct 11 '13 at 08:47

2 Answers2

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There's no reason the synthesiser shouldn't handle nested ifs and cases. And indeed I have done so many times in the past.

I imagine the algorithms of the synthesiser treats an if as just a 2-branch version of a case statement when it comes to logic implementation, so the type of decision function is not an issue. Nesting them will just cause it to create a set of logic for each decision, which is cascaded in the case of the nested decision.

If you find it doesn't work, file a bug report!

Of course, if you have very aggressive timing constraints, and many nested conditions, you may find that the logic the synthesiser produces, while correct, is not quick enough to meet your clock period target. In that case, there's nothing much for it but to refactor your logic to reduce the depth of the decisions.

Martin Thompson
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Annex J of IEEE Std 1076-2008 (the LRM) references IEEE Std 1076.6-2004, IEEE Standard for VHDL Register-Transfer Level (RTL) Synthesis, wherein case statements are supported and a case statement alternative (the actual choice and associated sequence of statements) may specify sequential statements including case statements.

So the answer is yes, you should in general expect to have cases statements in case statement alternatives be capable of being synthesized. Whether or not a particular vendor fully supports 1076.6 or not is a separate question.