Verilog : Use of 'PARAMETER during instantiation

Question

I am trying to understand a piece of Verilog code as below:

module_name instance_name (
.....
.signal1(signal1_local['SIGNAL_WIDTH - 1 : 0]),
....
);

I am not able to understand the 'SIGNAL_WIDTH , why is the apostrophe (') used here? Can anyone please tell what does it signify? Thanks in advance

It's a definition. Look up `define. – EML Oct 08 '13 at 10:44 — EML, Oct 08 '13 at 10:44

score 1 · Answer 1 · answered Oct 08 '13 at 10:49

1

It is a tick define:

Some where in the code there will be some thing similar to:

'define SIGNAL_WIDTH 10

They tend to be global, so it could be anywhere.

answered Oct 08 '13 at 10:49

Morgan

Morgan is correct. It's done this way because the code was written such that the signal: signal1 could change in ONE spot (at the `define location) and it would change the width of the signal in the rest of the code. It's good practice. – Russell Oct 08 '13 at 11:02

1 Answers1