Verilog: 3D synthesizable parameter

Question

Is it possible to create a synthesizable 3D parameter in Verilog?

I want to do something similar to this C style code:

parameter  [8][5]test [5] = {
{
 {0,  1,  2,  3,  4},
 {5,  6,  7,  8,  9},
 {10, 11, 12, 13, 14},
 {15, 16, 17, 18, 19},
 {20, 21, 22, 23, 24}
 },{
 {4,  3,  2,  1,  0},
 {9,  8,  7,  6,  5},
 {14, 13, 12, 11, 10},
 {19, 18, 17, 16, 15},
 {24, 23, 22, 21, 20}
 }...   
}

Answer 1

Verilog doesn't allow parameter arrays, so you're out of luck. SystemVerilog does, though.