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Is there any tool which will generate verilog RTL code which passes through the particular testbench? i.e. go from testbench to RTL

Is there any way to do it.

Morgan
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user1761275
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    This doesn't make any sense, I can't figure out what you are asking. – Tim Aug 28 '13 at 21:47
  • I am asking that is there any tool which can generate verilog code if we give verilog test bench as input to that tool? is there any way – user1761275 Aug 28 '13 at 22:02

1 Answers1

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No, I don't think that exists nor is it a good idea in my opinion for the following reasons to name a few:

  1. Verilog can be written in many ways
  2. Timing issues cannot be solved properly using algorithms
  3. Sometimes a testbench cannot, or is impractical to be exhaustive

There's probably many more.

However what I think you are looking for (in a more general sense) is something that converts truth tables into boolean expressions, and from there you can write Verilog with that if you want to.

BUT PLEASE DO NOT WRITE VERILOG IN THIS WAY THIS IS NOT WHAT TESTBENCHES ARE FOR

Try not to automatically generate any code unless you are using things like Megafunctions.

DevGoldm
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