Can someone explain to me what this master model command interface state machine means?
I am trying to add a custiom Ip to my design using Virtex-5 FPGA. I can see this in my USERLOGIC section. I have very little understanding of what this means.
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This may help: http://forums.xilinx.com/t5/New-Users-Forum/How-to-understand-master-model-command-interface-state-machine/td-p/347403 – Veridian Aug 14 '13 at 20:01
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than very much for link – user1107855 Aug 15 '13 at 16:33