x86 has had cases of the manufacturer inserting, new, undocumented opcodes at the time. Due to ARM holdings lack of a fab plant, there could be 'hidden' opcodes inserted by the licentiate. After using my google-fu this theory seems to be incorrect. From documentation, or past experiences -- do you know of any 'hidden mnemonics'?
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2HCF, perhaps is there. – Jiminion Aug 07 '13 at 15:54
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Not a hidden opcode, but I remember investing a bug once where a piece of hand-written NEON code would crash on one device which used a "vanilla" ARM implementation, while working just fine on another device that was based on one of Qualcomm's Snapdragon platforms. It turned out that according to ARM's specification, one of the instructions used in the code was only allowed to use the first 16 double-word registers as one of its operands. The Snapdragon apparently didn't care about this, but on the vanilla implementation it'd cause an exception. Can't remember which instruction it was. – Michael Aug 07 '13 at 16:17
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XScale can be a very visible example of such fork. Intel at the time added own instructions to provide a more media capable core.
From Intel XScale® Core Developer’s Manual:
2.3 Extensions to ARM Architecture
3rd generation microarchitecture extends the ARMv5TE architecture to meet the needs of various markets and design requirements. The following is a list of the extensions which are discussed in subsequent sections.
- A Media Processing Co-processor (CP0) has been added that contains a 40-bit internal accumulator. Five new instructions have been added which access the 40- bit accumulator. Page Attributes were added to the page table descriptors and the description of existing attributes in ARMv5TE were enhanced. Note that compatibility is maintained with software developed using page table attributes for previous microarchitectures.
- Co-processor 7 and Co-processor 14 registers are added to 3rd generation microarchitecture.
- Co-processor 15 functionality is extended and new registers are added.
- Enhancements were made to the Exception Architecture, which include instruction cache and data cache parity error exceptions, debug exceptions, and imprecise external data aborts.
Qualcomm at the writing time of this post is like Intel but with a more closed approach. May be they don't directly add new instructions to their cores but they try to modify them in a way to give them advantage over other ARM cores. An example to this is SIMD instructions, Qualcomm has its own co-processor called VeNum and that has some less limitations of register addressing as compared to ARM cores - read Michael's comment as an example.
