32 bits data_in and CRC7 VHDL code

Question

I would like to check if my code is correct for this

32 bits data_in
7 bits CRC

Please help me check and if possible explain me how does this code works.

library ieee;
use ieee.std_logic_1164.all;

entity CRC7_32 is
port (data_in : in std_logic_vector (31 downto 0);
crc_en , rst, clk : in std_logic;
crc_out : out std_logic_vector (6 downto 0));

end CRC7_32;

architecture behavior of CRC7_32 is

signal crc_block: std_logic_vector (6 downto 0);
signal crc_next_state: std_logic_vector (6 downto 0);

begin

crc_out <= crc_block;

crc_next_state(0) <= crc_block(5) xor crc_block(6) xor data_in(0) xor data_in(4) xor data_in(7) xor data_in(8) xor data_in(12) xor data_in(14) xor data_in(15) xor data_in(16) xor data_in(18) xor data_in(20) xor data_in(21) xor data_in(23) xor data_in(24) xor data_in(30) xor data_in(31);
crc_next_state(1) <= crc_block(6) xor crc_block(0) xor data_in(1) xor data_in(5) xor data_in(8) xor data_in(9) xor data_in(13) xor data_in(15) xor data_in(16) xor data_in(17) xor data_in(19) xor data_in(21) xor data_in(22) xor data_in(24) xor data_in(25) xor data_in(31);
crc_next_state(2) <= crc_block(0) xor crc_block(1) xor data_in(2) xor data_in(6) xor data_in(9) xor data_in(10) xor data_in(14) xor data_in(16) xor data_in(17) xor data_in(18) xor data_in(20) xor data_in(22) xor data_in(23) xor data_in(25) xor data_in(26);
crc_next_state(3) <= crc_block(1) xor crc_block(2) xor crc_block(5) xor crc_block(6) xor data_in(0) xor data_in(3) xor data_in(4) xor data_in(8) xor data_in(10) xor data_in(11) xor data_in(12) xor data_in(14) xor data_in(16) xor data_in(17) xor data_in(19) xor data_in(20) xor data_in(26) xor data_in(27) xor data_in(30) xor data_in(31);
crc_next_state(4) <= crc_block(2) xor crc_block(3) xor crc_block(6) xor data_in(1) xor data_in(4) xor data_in(5) xor data_in(9) xor data_in(11) xor data_in(12) xor data_in(13) xor data_in(15) xor data_in(17) xor data_in(18) xor data_in(20) xor data_in(21) xor data_in(27) xor data_in(28) xor data_in(31);
crc_next_state(5) <= crc_block(3) xor crc_block(4) xor data_in(2) xor data_in(5) xor data_in(6) xor data_in(10) xor data_in(12) xor data_in(13) xor data_in(14) xor data_in(16) xor data_in(18) xor data_in(19) xor data_in(21) xor data_in(22) xor data_in(28) xor data_in(29);
crc_next_state(6) <= crc_block(4) xor crc_block(5) xor data_in(3) xor data_in(6) xor data_in(7) xor data_in(11) xor data_in(13) xor data_in(14) xor data_in(15) xor data_in(17) xor data_in(19) xor data_in(20) xor data_in(22) xor data_in(23) xor data_in(29) xor data_in(30);

process (clk,rst)

begin

if (rst = '1') then
crc_block <= b"0000000";
elsif (clk'EVENT and clk = '1') then
if (crc_en = '1') then
crc_block <= crc_next_state;
end if;
end if;
end process;
end architecture behavior;

Work through the [PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS](http://www.repairfaq.org/filipg/LINK/F_crc_v3.html) until you understand the CRC process. Then do a small one on paper. Build the small one in VHDL. Make a testbench that checks it. When it works, try on the full-size CRC. — Martin Thompson, Jul 26 '13 at 09:27

score 0 · Answer 1 · 2013-07-26T07:35:02.677

I found a paper Cyclic Redundancy Code (CRC) Polynomial Selection For Embedded Networks http://www.ece.cmu.edu/~koopman/roses/dsn04/koopman04_crc_poly_embedded.pdf Which in Table 3 specifies CRC7 inverse as polynomial selection 0x44 and is 1+x^3+x^7.

OutputLogic.com has a CRC Generator that will output either Verilog or VHDL. Step 1, set the data width to 32, set the polynomial width to 7. The protocol is user defined because CRC7 isn't one of the predefined cases (and it sounds like a class assignment). Hit the Apply button and select Step 2. In Step 2, select X^1 and X^3 as polynomial coefficients, X^7 is assumed. Hit the Generate VHDL Code button, and you'll fairly quickly get a green message 'Code is generated'.

Let's just say it looks surprisingly like your code (and you should check the entire thing), and tells us what it produced in a comment -- lfsr(6:0)=1+x^3+x^7;

enter image description here

Whether or not the polynomial is correct may depend on a more authoritative source than the paper I found not to mention whether or not you should be using the other CRC7 definition, polynomial selection 0x48 (X^4 instead of X^3). There's also a Wikipedia entry on Cyclic redundancy check that sort of indicates you (we) have the right polynomial. It goes into what CRCs are a bit.

Once you've verified the polynomial your supposed to be using you can generate VHDL at OutputLogic.com, grab it, save to a file and because it's entity's name is crc by default you could write a testbench to compare the two with an assertion statement for various 32 bit test cases.

Or you could read through the two and compare them (hint you can change the names in one and do a white space ignoring diff).

Hi David, thank you for that advice. But how to understand the code that is generated as i am confuse on how the waveform is produce for this code. — user2617652, Jul 26 '13 at 08:14
I don't see how understanding CRC codes and/or targeting a particular word size can be accomplished (*Urgent). It isn't clear what you don't understand, CRC codes in general or how they are applied to a particular block size. The subject is outside the purview of the vhdl tag. — , Jul 26 '13 at 19:12

32 bits data_in and CRC7 VHDL code

1 Answers1