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MY PROBLEM

I have a SIMULINK model that has got a feeback loop aka Algebraic Loops that is causing error in the simulation. My original solver configuration was Fixed-Step with Dormand-Prince (Order 5). I also tried Fixed-Step with Order 3 (Runga-Kutta). It still has not resolved the issue.

MY QUESTION

Is there any way to resolve algebraic loop without altering the original performance or design of the circuit too much?

CLARIFICATION FOR THE QUESTION

I am sure that there will be a way to solve this. However, I don't want it to compromise the original performance of the circuit. Moreover, it is a customer-supplied data and it seems that they have managed to work this out as fine. I simply require somebody to point me to the right direction regarding how to solve this.

MY Approach so far

I tried to break the loop using:

i) Switch (if ip = 0, op = 0; if ip = 1, op = 1) I know it is stupid but it is a different block that breaks the loop.

ii) Logic gate (XORing the feedback signal with 0).

Unfortunately, I don't know how to do a zero-order hold unit delay loop that seems to be another commonly prescribed solution for this kind of problem. But I believe that may cause issues with my model's originally intended performance.

I have posted a query on Mathworks website, but no response so far. SO I thought...why not stackoverflow? Below is the image.

enter image description here

ha9u63a7
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2 Answers2

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Add a unit delay block on the feed back signal (from Logical Operator1 to Logical Operator4).

The unit delay provides the previous value of the output signal - this won't affect most of the circuitry in this scenario.

gary
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P0W
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  • hence my comment previously after @am304 answered :) – ha9u63a7 Jul 26 '13 at 07:04
  • @hagubear ouh you already figured out, cool ! I use delay block a lot to get rid of such scenario, the generated code also seems to be pretty acceptable, as the time gap between two cycles are very less. – P0W Jul 26 '13 at 07:08
  • Fortunately, the delay I implemented was very small...near the range of propagation delay of the gates, I hope it is okay.....I wonder if you would be interested in another problem I am trying to solve [here](http://stackoverflow.com/questions/17862816/implementation-of-custom-counter-logic-in-simulink) – ha9u63a7 Jul 26 '13 at 07:17
  • Sometimes works, sometimes oscillates. [Read This](http://blogs.mathworks.com/simulink/2015/07/18/why-you-should-never-break-an-algebraic-loop-with-with-a-memory-block/) – ar2015 Mar 07 '16 at 05:07
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There isn't a "one size fits all" answer when it comes to algebraic loops. Here are a few resources about algebraic loops:

In your case, I would suggest highlighting the algebraic loop (as per the doc in the hyperlink above), and try inserting a unit delay in the loop. The doc shows how to do this. Other suggestions would be to try the algebraic loop solver or model parameters related to algebraic loops, or placing an IC or Algebraic Constraint block in the loop. Again, refer to the doc in the hyperlink above for details. I assume you are constrained to use a fixed-step solver and cannot switch to a variable-step solver.

am304
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    I have resolved it by adding a delay block with a very miniscule delay. I know it is a compromise, but the delay is acceptable :) – ha9u63a7 Jul 25 '13 at 15:45
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    It's simply about breaking the algebraic loop. But sometimes adding a delay block or memory block won't even work because of multiple looping. – Akhil Nandan Oct 25 '22 at 15:33