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My Problem

I want to model a block called "confirmer". The specification is that the output will SIMPLY be the delayed version of input based on an edge (rising/falling). To clarify, I will try to put the timing diagrams below:

                 ___________________________ 
                |                           |
Input    _______|                           |____________________________

               (Tdelay) _____________________
                       |                    | 
Output   ______________|                    |____________________________

And

                        ____________________________
                        |                           |
Input    _______________|                           |____________________________
                                                      (Tdelay)                           
                        ______________________________________
                        |                                     | 
Output   _______________|                                     |_____________________

As I tried to draw above, the rising edge means that my output will simply follow the change input after Tdelay. But when it changes back from 1 to 0, there is no delay. This is the diagram for a confirmer block that is rising edge triggered.

For a falling-edge triggered confirmer, it is the opposite. When there is a falling edge, the output will follow the change in input after Tdelay seconds i.e. hold the last input for Tdelay.

My Target Platform

SIMULINK and MATLAB.

My initial solution

I know that there is way to trigger for certain actions by using a triggered subsystem block. But I am struggling to use the delay/unit-delay block in SIMULINK to implement the delay with the trigger. I have managed to use another block called resettable delayer but it does not work properly when it is a rising-edge reset; it simply resets based on an edge.

Has anyone tried this kind of problem before?

Update since @PhilGoddard's answer

enter image description here

I think this should work as I have managed to reproduce the timing diagrams in the question.

How I designed it:

1) Used the repeating sequence stair as my input.

2) configured the unit delay block such that the reset is enabled at rising edge or fallling edge. This will allow either of the following"

i) Input (falling edge) = Output (falling edge) [rising edge is delayed by Tdelay ii) input (rising edge) = Output (rising edge) [failling edge is delayed by Tdelay]

Unless I am losing my marbles, I think that this solution is okay?

ha9u63a7
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4 Answers4

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Use an Enabled and Triggered Subsystem.

Drag that block from the Ports and Subsystems library, and make only two changes to its properties: Open the subsystem, open the outport (called Out1), and change the "Output when disabled" property to "reset" and the "Initial Output" to 0.

Then, feed your input into the enable port; feed a delayed version of your input into the trigger port (which by default is set to be rising edge); and feed a constant block (with value=1) into the signal inport. The output of the subsystem should be as desired.

Phil Goddard
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  • Thanks for the answer +1. I have a question about feeding the delayed input to the trigger port. What kind of delay shall I be using? Is it going to be delayed by `Tdelay/Tsampling` number of samples? Could you please clarify? – ha9u63a7 Jul 22 '13 at 19:44
  • Also, I am struggling with the falling-edge triggered one! – ha9u63a7 Jul 22 '13 at 20:22
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This is my solution for case 2 of the proposed problem. The output is the sum of two signals of opposite value which is increased at every rising or falling edge of the trigger signal. It is very likely an overkill and there is probably a much easier solution but the proposed solution did not work for me and this did.

My solution:
my solution

How the counter is created (credit to How to create a counter in simulink):
counter

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Lorenzo Meneghetti
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Try On/Off delay. It perfectly meets your demand.

(There should be its icon but It seems that I cannot post image with under 10 reputation)

The description from the help page says:

The On/Off Delay block implements the following logic when the Select type parameter is set to On delay:

  • When the input becomes true, the output becomes true after a preset time delay. The output remains true as long as the input is true.

  • When the input is false or becomes false, the output becomes false with no delay.

  • When the Initial condition of previous input parameter is set to 1, and the input is true at t = 0, the output is true with no delay.

The On/Off Delay block implements the following logic when the Select type parameter is set to Off delay:

  • When the input becomes false, the output becomes false after a preset time delay. The output remains false as long as the input is false.

  • When the input is true or becomes true, the output is true with no delay.

  • When the Initial condition of previous input parameter is set to 0, and the input is false at t = 0, the output is false with no delay.

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Noah Tang
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falling edge delay

rising edge delay

YIN_SOF
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