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This is my first query in stack exchange so please bear with me. Almost all the questions which come to my mind already got resolved from the forum, but I cannot able to found this one.

I have made a simple device driver in Linux where in my_init() function I have written following code:-

spinlock_t mylock = SPIN_LOCK_UNLOCKED
static int __init my_init()
{
     unsigned long flags;
     printk("Testing spinlock\n");
     spin_lock_irqsave(&mylock, flag);
     printk("Grabbing spinlock and return\n");
}

Thus simply I am returning without releasing the spinlock.According to the theory and Linux source code, the Interrupt got disabled in ARM. So I seen CPSR register of ARM using debugger with 'I' bit gets masked and thus IRQ are disabled. However to my surprise the Linux prompt and even schedule() function are working as usual.

So my query is in Linux do we use IRQ mode only for some of the peripherals? If this is the case how can we guarantee perfect synchronization between Thread Context and Interrupt Context?

A bit detail about my Target : TI81xx Soc, Linux 3.2, Lauterbach Debugger.

Thanks

  • Maybe you have multiple cores and only one of them has IRQ disabled? – tangrs Jul 14 '13 at 10:35
  • @tangrs In TI81xx SoC we only got a single ARM Cortex A8 core along with other coprocessors, but we only use ARM cortex A8 for console, ethernet etc. I think all the Interrupt handling of ARM is done in SVC mode instead of IRQ mode. However, spin_lock_irqsave only disable the IRQ mode of ARM. – actiononmail Jul 14 '13 at 15:40
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    There is code that unconditionally enables interrupts; especially at **schedule** points. There is no way for the **scheduler** to work or *wait for interrupt/WFI* instruction of the *idle* task. This is not a **bug**; your code is a bug and Linux fixes it. You may see a message in the kernel log. The *spin_locks* still work; you can not mask `irqs` through the scheduler and other points. The idea of the **save** is to keep them locked if they previously were. – artless noise Jul 15 '13 at 01:45

0 Answers0