What is cache size and cache line size?

Question

I am trying to understand the following from a DTS file. Am very new to OS/Kernel.

cpus {
    #address-cells = <1>;
    #size-cells = <0>;

    PowerPC,8313@0 {
        device_type = "cpu";
        reg = <0x0>;
        d-cache-line-size = <32>;
        i-cache-line-size = <32>;
        d-cache-size = <16384>;
        i-cache-size = <16384>;
        timebase-frequency = <0>;   
        bus-frequency = <0>;        
        clock-frequency = <0>;      
    };
};

Can anyone provide brief explanation of the above?

I understand the following. cache block size or cache line size: the amount of data that gets transferred on a cache miss. instruction cache (I-cache): cache that can only hold instructions. data cache (D-cache): cache that can only hold data.

Also what does i-cache-line-size mean?

d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <16384>;
i-cache-size = <16384>;

In certain dts files there are comments like from boot loader as follows.

cpus {
#address-cells = <1>;
#size-cells = <0>;

    PowerPC,8313@0 {
        device_type = "cpu";
        reg = <0x0>;
        d-cache-line-size = <32>;
        i-cache-line-size = <32>;
        d-cache-size = <16384>;
        i-cache-size = <16384>;
        timebase-frequency = <0>;   // from bootloader
        bus-frequency = <0>;        // from bootloader
        clock-frequency = <0>;      // from bootloader
    };
};

How do i find out from which file in bootloader? Bootloader used is U-boot.

Thanks.

TheCodeArtist · Accepted Answer · 2013-07-19T09:10:04.337

The DTS snippet describes the PowerPC 8313 CPU.

From the Datasheet of PowerPC 8313,

7.1.5.2 Cache Units The e300c3 provides 16-Kbyte, four-way set-associative instruction and data caches. The cache block is 32 bytes long ...

Further more,

7.1.6 Bus Interface Unit (BIU) Because the caches are on-chip, write-back caches, the most common transactions are burst-read memory operations, burst-write memory operations, ...
... Memory accesses can occur in single-beat (1–8 bytes) and four-beat burst (32 bytes) data transfers on the 64-bit data bus.

Essentially the DTS snippet configures :

the cache-size (to 16KB)
to make complete use of the on-board cache
the line-size (to 32 bytes)
to effectively use the BIU for fastest possible transfers between the CPU and the on-chip cache.

Update: Regarding your query about where to start?...

The BEST book to start with is always the Technical Reference Manual of the processor in question. It will be filled with lot of jargon specific to your hardware that you will need to patiently go through and understand.
In parallel start brushing-up your understanding of the Linux Kernel with books like "Linux Device Drivers 3e", "Understanding the Linux Kernel" and "Professional Linux Kernel Architecture".
The boot-loaders are usually written with the hardware in mind and implemented using similar semantics as the Linux Kernel i.e. borrow heavily from it. Tons of stuff is available in random blogs all over the internet. Being active on Stackoverflow and mailing-lists like kernelnewbies is a good way to find them on regular basis.

Thank you so much TheCodeArtist. Now i understand from where they are filled. Thank you so much. But the jargons are very new. I am new to embedded systems. My reponsibilty is Boot, OS, Drivers. It is clear that harware knowledge is needed to understand the above mentioned stuffs. Can you kindly recommend some books for me to start on embedded(hardware,Os(kernel),boot,drivers)? — New to Rails, Jul 18 '13 at 06:31
Thank you so much TheCodeArtist. I just understood the following "to make complete use of the on-board cache and line-size (to 32 bytes)","to effectively use the BIU for fastest possible transfers between the CPU and the on-chip cache." Beautifully explained. You are my guru. At first I just thought that the numbers are taken from reference manual. Now I understand why these values. — New to Rails, Jul 19 '13 at 05:15

What is cache size and cache line size?

1 Answers1