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I am studying the BlackFin Processor Programming Reference and comparing it with the ARMv7-A architecture.

I noticed that BlackFin can have certain error detection features. For example, it can generate a HARDWARE error interrupt when:

• Bus parity errors
• Internal error conditions within the core, such as Performance
  Monitor overflow
• Peripheral errors
• Bus timeout errors

Taken from pg205 BlackFin Processor Programming Reference for ADSP-BF5xx processors.

Does the ARM Archicteture have this feature?

Thank you!

Timmetje
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ShaZam
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1 Answers1

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The classical ARM architecture (aka "A&R") supports the following hardware-related exceptions:

  • Undefined Instruction
  • Prefetch Abort (failure to fetch an instruction)
  • Data Abort (failure to read or write data)

The Cortex-M model support more granularity:

  • HardFault (generic fault, not covered by other cases)
  • MemManage (memory protection fault)
  • BusFault (memory access fault)
  • UsageFault (code-related faults: undefined instruction, invalid state etc.)

Specific chips may implement other errors. In case of non-core hardware, errors would typically be signaled as interrupts.

Igor Skochinsky
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  • I see that the undefined, prefetch and data abort errors are signaled as interrupts and the vector addresses can be found at the beginning of the code. What about the other errors you mentioned?Would those errors be signaled as Software Interrupts to the core? for your information, I am actually studying the cortex - A model. More specifically, the Arm Cortex A9. – ShaZam Jul 10 '13 at 08:54
  • @ShaZam these are hardware events, so they would be signaled as hardware interrupts (IRQs). Software interrupts are invoked by code (`SWI` instruction). – Igor Skochinsky Jul 10 '13 at 11:24