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Specifically I am asking if there are any advantages of fewer levels in a hierarchical design. Ex. 5 levels vs 6.

The only pro's/ cons I am seeing are readability and maybe faster compilation depending on the tools?

Thanks!

Sam
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    Please clarify what you mean by "levels of wrappers". Are you referring to flattened vs. hierarchical design? – Greg Jun 20 '13 at 18:05
  • Yes that is what I mean. Does levels of wrappers mean something else I am not aware of? – Sam Jun 21 '13 at 14:57
  • Thanks for clarifying your question. Typically when I hear "wrapper" mentioned, I think of a translation layer usually to rename pins or the order . One example is a module that contains one user defined primitive, this allows instantiation to use both connect by name and connect by order. – Greg Jun 21 '13 at 16:00
  • When I hear wrapper, on the other hand, I think of some module which has already been proven to function correctly, but its functionality needs to be expanded. You don't want to change a proven code, therefore you create "wrapper" which instantiates the proven module and adds the required functionality externally. – Vasiliy Jun 21 '13 at 20:13

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Ok, so it depends how you have your constraints set up and what tool you are using. So if you allow the tool (for sure xilinx's vivado and ise does this and cadence as well) to "flatten" your design upon compilation/synthesis/pnr(place and route) there should be no difference in performance between a flattened design and a hierarchical design. this is because the tool basically ignores the boundaries of the files when trying to combine logic and place luts and what not.

If you on the other hand generate a net list or even have a tool place them out and then try and then piece them together individually you could miss out on shared logic or be stuck with a less then optimal placing or routing situation.

overall if you are interested in performance of your design, let the tool do as much as it can, the more freedom you give it the better it works. So, if you use wrappers (a good idea for human readability ) make sure to give the tool the freedom by using the flatten options.

alex_milhouse
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    Thanks! I am using the flatten option but just wanted to verify that there wasn't something happening on a level I was not aware of. – Sam Jun 20 '13 at 22:38
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    Flattening a design can help reduce synthesised area, but adds complexity to gate level simulation. A highly optimised flattened hierarchy can make ECOs very difficult and error prone. – Morgan Jun 21 '13 at 09:27
  • Thanks Morgan! How does a flattened design reduce area? Is it easier for the tools to optimize the design within a level? I don't foresee using any ECOs but it is good to know for reference. – Sam Jun 21 '13 at 15:05
  • I had a colleague answer my question on synthesized area. - some tools perform bottom up synthesis where more levels can cause duplicate logic. Because the tool does not have the two levels in its optimization scope at the same time. – Sam Jun 21 '13 at 15:15
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I'm not going to answer your question about advantages of fewer levels of hierarchy, but I'm going to give you a general advice.

Do not think about advantages (in simulation time / area / power / anything else) of fewer levels of hierarchy when writing your design. The whole point of Front-End - Back-End separation is to allow Logic Designers to focus on functionality. The form of your design's hierarchy should be dependent upon functional considerations only (logic separation / clock domains / power domains / reset domains / etc). Create the best functionality you can, and let Back-End guys do their work (usually, they are good at it).

Vasiliy
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