Measurement system of response time of computer monitor - VHDL

Question

I'm in work placement and I have this subject in VHDL : Measurement system of response time of computer monitor. To succeed I thought about to put a photodiode in front of the monitor and switch in black and white every second the monitor to known the response time. But I don't know really how to make that, I use a spartan 3 connected at the monitor by VGA. I right a program I'm not sure if it's right, (I think it's wrong). I show you my program :

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.NUMERIC_STD.ALL

ENTITY Counter IS
        PORT(clk, rst : IN STD_LOGIC;
             sync, PhD : IN STD_LOGIC;
             s        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY Counter;

ARCHITECTURE Main OF Counter IS
SIGNAL q : UNSIGNED (3 DOWNTO 0);
BEGIN
    s <= STD_LOGIC_VECTOR(q);
    PROCESS (clk, rst) IS
        BEGIN
            IF rst='1' THEN
               q<=(OTHERS => '0');
            ELSIF RISING_EDGE(clk) THEN
                IF sync='0' THEN
                    q=q;
                ELSIF sync='1' THEN
                    IF PhD='0' THEN
                    q<=q+1;
                    ELSIF PhD='1' THEN
                    q=q;
                    END IF;
                END IF;
            END IF;
    END PROCESS;
END ARCHITECTURE Mai

n;

Tell me if you need something more maybe I forgot something. And tell me what you thing about my program.

score 0 · Answer 1 · answered Jun 18 '13 at 11:30

What you wrote is a counter that is incremented in each clock cycle that sync is 1 and phd is 0. Without knowing your exact requirements, it is difficult to say whether this is what you want or not.

If you want to determine the amount of time between sync going high and phd going high, you should set q to 0 when sync=0. This will cause the counter to start from 0 each time sync goes high.

You should probably also increase the width of q, depending on how fast your clock is. Currently it has only 4 bits, meaning it will wrap back to 0 every 16 cycles. Given typical clock frequencies (e.g. 100 MHz), this is less than a microsecond. To count for one second at 100 MHz, you would need a counter of at least 27 bits.

yes sorry I forgot to say how I see my program, I want a program that count the time between the sync pass at 1 and the PhD pass at 1 too. I try to explain more specifically (My english is not very good :s) So every second I would like sync switch between 1 and 0 with a picture black and white. When the sync pass at 1 a counter count the time that the PhD receive the signal (pass at 1) to stop the counter. Ok I thought that I need just few bits because I know that this response time is very very fast. And I have to change this line : IF sync='0' THEN q=q; at q='0'; thanks for your help! — Vincent. L, Jun 18 '13 at 12:21

Measurement system of response time of computer monitor - VHDL

1 Answers1