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I understand that to set them, we need to append the S, e.g.

ADDS R0,R1,R2

which will for example, set C if the result overflows.

  • Am I correct in saying:

another line of code subsequent to the previous line such as:

SUB R3,R4,R5

will make NO CHANGES whatsoever to the condition flags? (due to the lack of S )

  • Subsequently, the next change in condition flags, regardless of the #lines of code can ONLY happen in the next line with the operation that has S appended?

  • Furthermore, the previous state of the condition flag bits make no effect on how the condition flags are set as they will be cleared or set depending entirely on the result of the current operation.

What if the result of the current operation does not affect some condition bits? For example

ANDS R0,R1,R2

only have N,Z flags relevant to them as the result cannot generate a carry C or a signed overflow Z. In such a case, will the C,Z flags be preserved or cleared?

To see when they are set is straightforward, but I find the lectures and books I am looking at very vague in describing precisely when they can get cleared so I asked a question here to get something concrete.

midnightBlue
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  • Don't think of the flags as being "set" or "cleared"...think of them as being updated. When updated, a flag can be forced to either a 0 or a 1 state. So, any instruction that updates the flags may either "set" or "clear" them. –  Jun 16 '13 at 23:24

3 Answers3

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Usually yes, only the instructions with the S suffix change the flags. However, there are a few exceptions to the rule:

  • TST/TEQ and CMP/CMN instructions update flags even though the mnemonic doesn't include S.

  • In the original Thumb syntax (pre-UAL), the S suffix was omitted but most ALU instructions did change the flags. In UAL, the S suffix must be explicit for both ARM and Thumb instructions.

  • Some instruction can operate on the APSR/CPSR register directly, e.g.:

    MSR APSR_nzcvq, #0x80000000 ; set N flag, clear others

    VMRS APSR_nzcv, FPSCR ; load floating-point status word into ARM flags

    (MRC can do it too, but coprocessor usage besides VFP/NEON is deprecated)

  • exception returns (RFE, LDM or SUBS PC, LR) can change the CPSR (and thus the flags) at the place where they return to.

Igor Skochinsky
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2

This should answer your question: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204j/Cihbjcag.html.

It seems that the condition flags are never really 'automatically' reset after a certain time. They can only be updated by instructions capable of doing so. This is my understanding of:

"In ARM state, and in Thumb state on processors with Thumb-2, you can execute an instruction conditionally, based upon the ALU status flags set in another instruction, either:

  • immediately after the instruction that updated the flags

  • after any number of intervening instructions that have not updated the flags."

arch904
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Please read the ARM manuals.

How is this vague?

if S == 1 then
N Flag = Rd[31]
Z Flag = if Rd == 0 then 1 else 0
C Flag = shifter_carry_out
V Flag = unaffected

Each of the flags is clearly defined. Unaffected means unaffected, it isnt touched whatever was there before will be there after. the rest are modified by ANDS

Likewise:

If S is omitted, the S bit is set to 0 and the CPSR is not changed by the instruction.

what is vague about "not changed by the instruction"?

old_timer
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  • Could you please reference where you got that from? What do you mean by V flag = unaffected? By which operation will it be unaffected? By vague, I was firstly referring to my lecture material which didn't have a clearly defined list in the format if(x)=y. But for example, you say that if the S bit is omitted, the CPSR is not changed by the instruction, but (if I understand it correctly) it is not true always. For example commands such as TEQ and CMP omit the S but do change the CPSR. I am looking for a concrete understanding especially since I have an exam coming up regarding this. – midnightBlue Jun 13 '13 at 15:29
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    It doesnt not matter what processor you are studying or using, go to the processor vendor or inventor and get their documentation. For arm docs you go to arm. Arm does a pretty good job, and has pseudo code descriptions for each instruction, so if you want to know how tmp and cmp and and and add and sub compare as far as flags, you have to look at each of them separately. – old_timer Jun 14 '13 at 00:19