Can somebody help for 5x7 dot matrix display simple VHDL code for charachter "R"?

Question

This is the code that I am using but i need to slow the clock down in order to see how the columns and rows are changing. I think there is some problem on my clocking:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dot_matrix is

  port (main_clk, en : in std_logic;


        switches : in    std_logic_vector (3 downto 0);
        rows     : inout std_logic_vector (6 downto 0);
        col      : inout std_logic_vector (4 downto 0));

end dot_matrix;

architecture Behavioral of dot_matrix is

  signal row_count  : std_logic_vector(2 downto 0);
  signal counter    : integer range 0 to 25000000 := 0;  -- to divide the clock down
  signal slow_clock : std_logic                   := '0';

begin

  clockdiv1 : process(main_clk)
  begin
    if main_clk'event and main_clk = '1' then
      if counter = 24999999 then
        counter    <= 0;
        slow_clock <= not slow_clock;
      else
        counter <= counter + 1;
      end if;
    end if;
  end process clockdiv1;

  SM : process (slow_clock)
  begin
    if (slow_clock'event and slow_clock = '1') then
      if (en = '1') then
        if (row_count = "100") then
          row_count <= "000";
        else
          row_count <= row_count + 1;
        end if;
      else
        row_count <= "000";
      end if;
    end if;
  end process SM;



  DIS : process (row_count)
  begin

    if row_count = "000" then           --1st clock count
      col  <= "01111";                  --selecting 1st column
      rows <= "1111111";                -- putting the data on the 1st column

    elsif row_count = "001" then        -- 2nd clock count
      col  <= "10111";                  -- selecting 2nd column
      rows <= "1001000";

      row_count = "010" then            -- 3rd clock count
        col  <= "11011";                -- selecting 3rd column 
        rows <= "1001100";

      elsif row_count = "011" then      -- 4th clock count
        col  <= "11101";                -- selecting 4th column 
        rows <= "1001010";

      elsif row_count = "100" then      -- 5th clock count
        col  <= "11110";                -- selecting 5th column 
        rows <= "0110001";

        -- 1 1 1 1 0

        -- 1 0 0 0 1

        -- 1 0 0 0 1

        -- 1 1 1 1 0

        -- 1 0 1 0 0

        -- 1 0 0 1 0

        -- 1 0 0 0 1

      end if;
  end process DIS;

end Behavioral;

EDIT: needed to add some text after fixing the Indentation of the code.

score 0 · Answer 1 · answered Jun 06 '13 at 11:05

0

There is a missing "elsif" in the line

row_count = "010" then

maybe that fixes your Problem already.

answered Jun 06 '13 at 11:05

youR.Fate

796
4
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29

score 0 · Answer 2 · answered Jun 06 '13 at 12:31

0

You are using an initial value '0' for your slow clock. You need to verify if your synthesizer and target technology support this. Some FPGA's do, some don't. Alternatively, you can add a reset signal and set a value when reset is enabled.

Other comments:

As youR.Fate says: you need an elsif halfway in your code.
Don't use IEEE.STD_LOGIC_ARITH and IEEE.STD_LOGIC_UNSIGNED. They are not standard. Use ieee.numeric_std instead. More info on: http://www.sigasi.com/content/deprecated-ieee-libraries

answered Jun 06 '13 at 12:31

Philippe

3,700
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Would it even compile with that elsif missing? I don't think so. Also, umid_uz never stated what does not work in his code. – youR.Fate Jun 07 '13 at 20:23
No, it does not compile with the elsif missing. – Philippe Jun 08 '13 at 10:05

Can somebody help for 5x7 dot matrix display simple VHDL code for charachter "R"?

2 Answers2