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I'm trying to design of an analyzer/simulator for a simplified MIPS CPU using a high level programming language preferably Java. The considered MIPS CPU adopts the CDC 6600 scoreboard scheme to dynamically schedule instruction scheduling and using cache for load and store instruction for cache hit and cache miss. I need some start up advice for this simulation.

Should I use Event Queue for this simulation? If so how?

Sina
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A simple RISC processor can be simulated by executing one instruction at a time. This is true even for a pipelined CPU.

Since you want to model a superscalar processor, where several instructions are in flight at the same time, an event based simulator will be the best way to correctly model which instruction completes when, and how the in-flight instructions compete for processor resources.

markgz
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  • thanks, Can you explain a little a bit more, what events should look like ? So, if using Object Oriented Programming, what does the class event look like? – Sina Apr 21 '13 at 19:02