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Trying to understand the cause of the watchdog. The snippet of assembly routine is as follows:

fe813cf0:       2820            cmp     r0, #32
fe813cf2:       dbf0            blt.n   fe813cd6 <XYZ+0x10>
fe813cf4:       f04f 30ff       mov.w   r0, #4294967295 ; 0xffffffff
fe813cf8:       bd10            pop     {r4, pc}

My PC value from dump is fe813cf3. What does this mean? How should I interpret it? Please let me know if more info is required.

Lundin
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Sandeep
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1 Answers1

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If it's a watchdog that triggers, that seems to indicate that the processor has hung. The state you're capturing might be corrupt, in the worst case. Not sure how you get the "dump", so it's hard to tell.

In general on ARM, an odd address indicates a jump that wanted to switch to the Thumb instruction set.

See for instance this documentation of the BX (branch exchange) instruction:

The BX instruction branches to the address contained in a specified register. The value of bit 0 of the branch address determines whether execution continues in ARM state or Thumb state.

Bit 0 of an address can be used in this way because:

  • All ARM instructions are word-aligned. This means that bits 0 and 1 of the address of any ARM instruction are ignored because these bits refer to the halfword and byte part of the address.

  • All Thumb instructions are halfword-aligned. This means that bit 0 of the address of any Thumb instruction is ignored because it refers to the byte part of the address.

However, I'm pretty sure the above implies that the PC is never actually set to an odd address, bit 0 is cleared by the branch instruction.

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unwind
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  • Am sure dump is not corrupted. For different use cases, like general crashes aswell ,i see that the address is odd number in pc. I am trying to figure out.. But the information you gave was useful. thank you – Sandeep Apr 18 '13 at 10:46
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    The reason that you see the odd number in dump's PC is because the exception handler gets the PC value from the LR register which is where the PC gets stashed when the exception is triggered and the CPU vectors to the handler. If the CPU was in thumb mode when the exception happened, LR will have bit 0 set. Note that due to the pipeline effect, the PC that gets stored into LR will be a couple instructions after the faulting instruction (so I think that the instruction that caused the fault would be at address 0xfe813cee - probably a load of `r0` from an invalid address). – Michael Burr Apr 26 '13 at 21:59