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I have one question about the timing of interrupt generation between code snippets...

@ "example" code

1. ...
2. assign value to global variable  // 0/1 means invalid/valid
3. set H/W register via memory-mapped IO method  // 0 means completed

@ "example" ISR code

a. ...
b. if(global value is valid && H/W register is "0") then count++;
  • One thing to note: After H/W register is set, its value will be 0 when "completion" !

My question is: if the interrupt is generated between 2 and 3, then count will be increased by one because step 3 is not done yet(value is 0)... And if exchange 2 and 3, then it is possible count will NOT be increased by 1 because even HW register is 0(after some time, completed) global variable is 0 !

My first idea is: is it possible 2 and 3 can be "tied together" in some way and interrupt is not allowed to be generated until 3 is done ?

  • I use watcom c and test in DOS...
liaoo
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1 Answers1

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You can use either inline assembly, or a call to an external function written in assembler, to invoke the x86 CLI and STI instructions for disabling and enabling interrupts.

R.. GitHub STOP HELPING ICE
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    you mean `cli+2+3+sti` can be written as inline assembly or external assembly function ? Does that means interrupt will not assert during these assembly codes ? – liaoo Apr 09 '13 at 03:12
  • As long as the `cli` takes place in assembly that runs before steps 2 and 3, and the `sti` takes place in assembly that runs after steps 2 and 3, you should be good. – R.. GitHub STOP HELPING ICE Apr 09 '13 at 03:28
  • Finally I just mask the interrupt device used(instead of masking "all" maskable interrupts) to make other interrupts work well by configuring 8259s... – liaoo Apr 09 '13 at 06:15
  • The above method is OK with pin-based interrupt mode. But if using MSI(Message Signaled Interrupt) how to "enable/disable" MSI for this purpose ? – liaoo Apr 12 '13 at 07:16
  • Huh? Pin-based versus MSI should only matter at the hardware level. Clearing the interrupt flag (via `CLI`) prevents the cpu from acting on any interrupts. – R.. GitHub STOP HELPING ICE Apr 12 '13 at 07:26
  • As I know sti/cli configures IF(Interrupt flag) and determines whether or not the CPU will handle maskable hardware interrupts. Here the maskable interrupts means 8259's IRQ 0~15, right ? But for MSI, this kind of interrupt is issued via CPU's local apic and does not route 8259. Thus I guess sti/cli can not "block" MSI... – liaoo Apr 24 '13 at 07:25