0

I have some strange problem, some wires are not connected in my design.

I am trying to make a simple register file (I am using Xilinx ISE). This register file contains 32 registers, each is 32-bit size. The register file has two MUXs for reading selection (2 readings in parallel), and a decoder for write selection. When I try to connect signals from each register to the 2 MUXs, the signals appear in the RTL connected to only one of the MUXs. For example, let signal reg2out be the output of reg2. I connect reg2out to pin I1 of mux1, and connect again reg2out to pin I1 of mux2. The RTL then shows the second mux connected correctly, but the first mux appears with no inputs, no selectors, and no output connected to it. The next image shows the RTL. problem

Note: ISE generates the following warning when synthesizing

"WARNING:Xst:1348 - Unit mux is merged (output interface has tristates)"

which I don't understand.

The main module source "RegisterFile.vhd" can be found here. I have tried a dozen of modifications to correct, including adding new signals, storing the registers output in D-FFs, and storing the registers output in process variables; and the problem still existing. The design contains two other files: "dec.vhd", and "mux.vhd". I believe the design of these modules is correct.

How can I correct the problem? Is it a bug in ISE rather?

  • it seems that ISE combines your MUXs... can you also make dec.vhd, mux.vhd and "mine"-package available to reproduce the issue? are read_sel1 / read_sel2 generated individually or in anyway depending on each other? – baldyHDL Mar 28 '13 at 06:43
  • @baldyHDL Find the rest of files here http://ideone.com/89wHMA –  Mar 29 '13 at 03:45
  • using ISE13.4 with default synthesize properties, I get both MUXs. this means, I can not reproduce the issue! again, are read_sel1 and read_sel2 external signals (FPGA inputs) or are they generated inside your code and somehow related to each other? – baldyHDL Mar 29 '13 at 06:10
  • @baldyHDL Yes, read_sel1 and read_sel2 are external signals (as you can see in file "RegisterFile.vhd" –  Mar 29 '13 at 06:12
  • ok, so what ISE version do you use? as I couldn't reproduce the issue with 13.4. btw, it's not obvious that RegisterFile is the top level of your whole FPGA design ;-) – baldyHDL Mar 29 '13 at 06:35
  • From about menu `Project Naviagtor Release Version: 12.1 (nt) Application Version: M.53d` –  Mar 29 '13 at 06:38
  • I doubt that it's a bug as the task is simple and common. just to make sure we have no misunderstanding: RegisterFile is directly connected to fpga pins? If otherwise sel signals are related in any manner, the synthesiser can optimize/trim stuff. the synthesiser doen't bother about hierachical borders (unless you set that option explicitely!) – baldyHDL Mar 29 '13 at 07:33
  • The main module is RegisterFile.vhd. Its input are the inputs of the FPGA. The complete code you have got, there is **NO** more code with me you didn't see. I can upload the entire project for you if you want –  Mar 29 '13 at 07:42
  • thanks for the clearification! I can reproduce the issue with 12.1 too. however, already with 12.2 it's not reproducable. It therefore indeed looks like a bug in 12.1. checking the Synthesis report one can see that two 32 bit 32 to 1 multiplexers are found... it might therefore be a bug only in RTL schematic visualisation! – baldyHDL Mar 29 '13 at 18:17

1 Answers1

1

it is a bug in ISE 12.1. however, it seems that it is only a bug in RTL schematic visualization, as the synthesis report mentions the used components correctly. using ISE version 12.2, the issue is not reproducible anymore.

baldyHDL
  • 1,387
  • 1
  • 10
  • 16