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I am stuck with the following situation

I am designing a vhdl project for uart. There are two components namely uart_rx.vhd and uart_tx.vhd.

I suppose uart_tx goes in Mark state initially upon receiving the value '0' to signal: ready. Signal Ready is uninitialized, i.e. ready = 'U'.

uart_tx waits for input from uart_rx.vhd. As soon as uart_tx receives '0' from uart_rx, FSM goes to Start instead of Mark.

Here is the algorithm I've used:

if ready = o
    state <= Mark
else
    state <= Start
Cezar
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Muss76
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1 Answers1

0

Write a testbench and an initialisation for ready:

signal ready : std_logic := '0';
user2099996
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  • Thank you for your answer. My problem is that signal ready is not in port list of top entity but it is in port list of component uart_tx. Individual simulations for both component entities work fine but when I used top entity with inputs going first in uart_rx and from there to uart_tx. Finally output from uart_tx goes to output of top entity. Any solution ... – Muss76 Mar 18 '13 at 05:29
  • define the signal in your top module (between _architecture..._ and _begin_) as shown in the answer. – baldyHDL Mar 18 '13 at 08:48
  • I succeeded. Actually I've just changed order of if else. Previously I used: if Ready = '0' then ... else ...... Now I used If Ready = '1' condition first. Doing so my problem is resolved. It seems that there are microscopic bugs or limitations with ISim simulator (8.2i). I would like to share more info if I find some useful info. Thanks all guys – Muss76 Mar 18 '13 at 12:06
  • If you're using ISIM 8.2 ... wow. ISIM started to turn into a buggy but usable simulator around 10.1, as of 13 or 14 it's not too bad. But 8.2 ... wow! If you possibly can ... I heartily recommend an upgrade! –  Mar 19 '13 at 15:26