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I'm reading, in a simple way, how do TLBs work and I don't understand something:

The TLB references physical memory addresses in its table. It may reside between the CPU and the CPU cache, between the CPU cache and primary storage memory, or between levels of a multi-level cache. The placement determines whether the cache uses physical or virtual addressing. If the cache is virtually addressed, requests are sent directly from the CPU to the cache, and the TLB is accessed only on a cache miss. If the cache is physically addressed, the CPU does a TLB lookup on every memory operation and the resulting physical address is sent to the cache.

Summary: When the TLB is between CPU and CPU cache it uses physical addressing and the CPU does a TLB lookup on every memory operation and the resulting physical address is then sent to the cache.

My question: since the CPU deals with virtual addresses, how is this query performed?

I don't understand: CPU encounters a virtual address -> CPU contacts TLB which is addressed with physical addresses -> ?? -> TLB spits out another physical address

TLB:

| Physical Address | Another Physical Address |

This totally doesn't make sense to me

Taken from wikipedia

Leeor
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Johnny Pauling
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3 Answers3

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Where did it say that the TLB is physically addressed?
The TLB is of course translating from virtual to physical, when the cache is physically addressed then you get this flow: Memory unit runs in virtual addr space (except for pagewalks and TLB maintenance) --> TLB translates V->P --> cache lookup is done with physical address.

TLB:

| virt Address | Physical Address |

Cache:

| Physical Address |        Data           |

The section above just says that if the cache is physically addressed as here, you need a TLB lookup on every access (before you even know if you hit/miss), while if the cache is virtually addressed, you can lookup the cache before translating, and only go to the TLB if you missed and need to go to memory / lower (physically addressed) cache

Leeor
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According to me CPU will always lookup TLB when there is a cache miss... CPU will not know on its own that whether the address is virtual or physical address.. therefore CPU---> CPU cache--->(if cache miss) TLB--->(if TLB miss)--->secondary memory

while fetching the page.. TLB entry, CPU cache will be updated with this recent entry..

tanmayub
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  • Your point makes sense to me and that's the "virtual addressing" method. But my question is on the physical addressing method that, in my humble opinion, doesn't make sense. – Johnny Pauling Mar 14 '13 at 11:25
  • ohh my bad.. on a more related topic.. As for what I know... If a CPU is using physical addressing then there wont be any TLB present.. processor will directly fetch the data from that address.. – tanmayub Mar 14 '13 at 11:34
  • And that also perfectly makes sense too! I agree with you, I'm just wondering why wikipedia cites TLB "physical addressing". Meh.. – Johnny Pauling Mar 14 '13 at 11:39
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The TLB gets the virtual address from the CPU. This adresses' bits can be split into the Virtual Page Number and Virtual Page Offset.

The Virtual Page Offset corresponds to the Physical Page Offset. The Virtual Page Number is split into a Tag and an Index. Based on the Tag and Index, the TLB checks in its own cache what Physical Page Number it is and assuming it was already in the TLB cache and marked as valid, it is returned back to the Cache with the Physical Page Number as Cache Tag and the Physical Page offset split into Cache Index and Cache Offset. This is then used to to check whether itis already in that cache (and if not, is loaded from disk) and finally returns the values.

I hope this is correct and answers your question, I'm currently still learning about the topic of the TLB too, so please do not take this answer for completely correct. However, it should give you a good overview.

lucidbrot
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