Is it possible to have generic type in vhdl?

Question

Is there a way in VHDL to have generic types? So for example I want to call a procedure but I'm not sure what type the signal has I want to give as paarameter, is it possible to declare the parameter as generic? Like in C++ you would use a Template.

procedure eq_checker(name : string; sig : ANYTHING); should : ANYTHING; at : time) is
  if (at = now) then
    if sig = should then
      report "has same value" severity note;
    else
      report "has not same value" severity note;
    end if;
  end if;
end checker;

At least it should be possible to use different signal types as "sig".

score 6 · Accepted Answer · 2013-03-13T13:18:33.553

6

The Peter Ashenden and Jim Lewis book "VHDL-2008 - Just the new stuff" opens with

Chapter 1 : Enhanced Generics
1.1 Generic Types

So, if your tool supports VHDL-2008 properly, you can now declare generic types, and you can declare generics on subprograms (not just entities).

And if they have followed the Ada model, the generics will be checked when you first compile them, not when you instantiate them, so that any instantiation that compiles will work, unlike the situation with C++ templates where bugs can lie dormant for years until you instantiate them in a particular way (because C++ templates are closer to macros than true generic metaprogramming)

Example : untested, but written following examples on p.17 of aforementioned book...

procedure eq_checker
         generic  (type ANYTHING) 
         parameter(name : string; sig,should : ANYTHING; at : time) is
begin
  if (at = now) then
    if sig = should then
      report "has same value" severity note;
    else
      report "has not same value" severity note;
    end if;
  end if;
end procedure eq_checker;

edited Mar 13 '13 at 13:18

answered Mar 13 '13 at 11:07

Thanks. Im going to see if this really solves my problem. But I hope so – Sadık Mar 13 '13 at 11:37
1

If you find specific VHDL-2008 features not supported by your tools, please (a) update the question (or comment) with what's missing and (b) report them as bugs to the tool vendors. Also be aware that simulation and synthesis may deliver different levels of support. – Mar 13 '13 at 11:40
thank you! It seems that Modelsim in my version does not support generic types unfortunately. They don't say that it is not supported, but they also don't say that it is supported. And they give me a simple `near "generic": syntax error` – Sadık Mar 14 '13 at 10:03
Check the Modelsim docs; there will be command line options to "vcom" allowing you to select different VHDL versions : something like `vcom -2008 myprog` to select VHDL-2008 – Mar 14 '13 at 10:34
Yeah, I did that. But my modelsim version really does not support VHDL 2008 fully. I'm using Modelsim SE 6.6d. – Sadık Mar 14 '13 at 10:42
Then filing a bug report won't help : current Modelsim is 10.something, 6.6 is an antique. – Mar 14 '13 at 10:45

score 1 · Answer 2 · answered Mar 13 '13 at 15:41

if you don't know the type in the very moment you write e.g. a procedure, you can use a subtype. you can always change the subtype before synthesis. ok, this is only "somewhat generic" but still... it could look like that:

PACKAGE generics_pkg IS
-- type definition
subtype data_type is integer;

-- instantiation
COMPONENT generics IS
PORT(
    i: IN data_type;
    ii : in data_type;
    o: OUT std_logic    
);
END COMPONENT;

-- procedure
procedure comp (    signal x,y: in data_type; 
                    signal o: out std_logic);

END PACKAGE generics_pkg;

package body generics_pkg is
procedure comp (    signal x,y: in data_type; 
                    signal o: out std_logic) is
begin
    if x = y then
        o<='1';
        report "same value" severity note;
    else
        o<='0';
        report "not same value" severity note;
    end if;
end procedure comp;

Thanks, but this way I can call eq_checker only for one type. But I want to call it at many different states and for many signals of different types — Sadık, Mar 14 '13 at 10:00
couldn't you use type-conversions like **to_integer** or **to_unsigned** to adjust your parameters to the needs of your procedure as soon as you call it? this way you could write your procedure for one parameter-type but use it from different states with different types! — baldyHDL, Mar 15 '13 at 07:05

Is it possible to have generic type in vhdl?

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