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I am writing some bare metal code for the Raspberry Pi and am getting an unexpected warning from the ARM cross assembler on Windows. The instructions causing the warnings were:

stmdb sp!,{r0-r14}^

and

ldmia sp!,{r0-r14}^

The warning is:

Warning: writeback of base register is UNPREDICTABLE

I can sort of understand this as although the '^' modifier tells the processor to store the user mode copies of the registers, it doesn't know what mode the processor will be in when the instruction is executed and there doesn't appear to be a way to tell it. I was a little more concerned to get the same warning for:

stmdb sp!,{r0-r9,sl,fp,ip,lr}^

and:

ldmia sp!,{r0-r9,sl,fp,ip,lr}^

despite the fact that I am explicitly not storing ANY sp register.

My concern is that, although I used to do a lot of assembler coding about 15 years ago, ARM code is new to me and I may be misunderstanding something! Also, if I can safely ignore the warnings, is there any way to suppress them?

williamssimonp
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2 Answers2

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The ARM Architecture Reference Manual says that writeback is not allowed in LDM/SMT of user registers. It is allowed in the exception return case, where pc is in the register list.

LDM (exception return)

LDM{<amode>}<c> <Rn>{!},<registers_with_pc>^

LDM (user registers)

LDM{<amode>}<c> <Rn>,<registers_without_pc>^
Variable Length Coder
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  • So, to return from an exception using the first form, you have to do the storing of the registers without writeback, update the stack pointer and then you can use version with writeback to return! The restriction seems a little odd, but I'm sure there's a reason for it. At least it allows writeback if pc is being loaded, otherwise it would be useless! – williamssimonp Mar 13 '13 at 15:59
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The term "writeback" refers not to the presence or absence of SP in the register list, but to the ! symbol which means the instruction is supposed to update the SP value with the end of transfer area address. The base register (SP) value will be used from the current mode, not the User mode, so you can still load or store user-mode SP value into your stack. From the ARM ARM B9.3.6 LDM (User registers):

In a PL1 mode other than System mode, Load Multiple (User registers) loads multiple User mode registers from consecutive memory locations using an address from a base register. The registers loaded cannot include the PC. The processor reads the base register value normally, using the current mode to determine the correct Banked version of the register. This instruction cannot writeback to the base register.

The encoding diagram reflects this by specifying the bit 21 (W, writeback) as '(0)' which means that the result is unpredictable if the bit is not 0.

So the solution is just to not specify the ! and decrement or increment SP manually if necessary.

Igor Skochinsky
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  • Ah, I had missed that bit in the Architecture Reference Manual, although I must admit that I have been using the ARM1176JZF-S Technical Reference Manual for most of my information and that doesn't seem to go into that much detail! All the explanations of the warning I found using Google (not many!) say that the warning is caused because you are doing a writeback to a register that is being loaded/stored. I understand that the writeback refers to the updating of the base register. – williamssimonp Mar 13 '13 at 09:04