-1

I'm new to VHDL and I'm having a problem with my code that I can't seem to fix. We're supposed to do this using either selected signal assignment or table lookup. Mine is kind of a combination of the two since we are supposed to use don't cares for inputs that will not happen.

The code is basically supposed to give the same output for either 2's complement input or offset binary. So, for instance, decimal number 7 is "1111" in offset binary and "0111" in 2's complement. Both forms should generate an output of "1111100000" depending on the value of the switch oe ('1' for offset binary, '0' for 2's complement).

I've debugged my code as much as I can at this level and I do not understand what I'm doing wrong.

Active-HDL is currently giving me errors at lines 48 and 55. I'm getting two "simple expression expected" errors.

My code is at the pastebin URL below since it allows for better readability and syntax highlighting (plus, I don't like fiddling with Stack Exchange's odd ways of posting code). Also, if you have any tips on how I can improve the code while maintaining the assignment instructions, please feel free to suggest anything.

http://pastebin.com/aAJAs6KQ

audiFanatic
  • 2,296
  • 8
  • 40
  • 56
  • Exact duplicate of http://electronics.stackexchange.com/questions/59097/vhdl-error-simple-expression-expected –  Feb 25 '13 at 15:17

1 Answers1

0

Just use a process to make it more readable:

...
-- untested
process( input, d, tmp, ob)
begin
   if ob = '1' then  
        led <= table(to_integer(unsigned(d & tmp)));
   else                 
        led <= table(to_integer(unsigned(not d & tmp)));
   end if;
end process;
...
user2099996
  • 124
  • 3