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I am writing a test bench for Ripple counter using d flip flop. My program is compiling without errors, however, I get undefined result. How can I solve this problem?

Here is the code:

module RCounter;

reg d,d2,d3,d4,clk;
wire q,q2,q3,q4;


DFlipFlop a(d,q,clk);
DFlipFlop a1(d2,q2,q);
DFlipFlop a2(d3,q3,q2);
DFlipFlop a3(d4,q4,q3);

initial

begin

clk =1;


d=0;d2=0;d3=0;d4=0;

#2 d=1;d2=~q2; d3=~q3; d4=~q4;
#2 d=0;d2=~q2; d3=~q3; d4=~q4;
#2 d=1;d2=~q2; d3=~q3; d4=~q4;
#2 d=0;d2=~q2; d3=~q3; d4=~q4;
#2 d=1;d2=~q2; d3=~q3; d4=~q4;
#2 d=0;d2=~q2; d3=~q3; d4=~q4;
#2 d=1;d2=~q2; d3=~q3; d4=~q4;

end

always 
begin

#2 assign clk = ~ clk;

end

endmodule

What am I doing wrong and how can I solve this?

Tim
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James Aflred
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1 Answers1

2

What you have there is not a ripple counter, and it seems that you don't really understand the boundary between your testbench and your DUT (design under test, or in your case, the 'ripple counter').

What you have is a testbench that is simulating four independent flip flops. If you were simulating a ripple counter, you should have a module called something like 'RCounter', which is instanced inside something else called 'RCounter_TB'. The testbench should only drive the inputs (for a counter, clock and reset), it should not drive the d pins of the individual flops, as the connections between these flops is what you want to test.

Inside the ripple counter module, you define the wired connections between your flip flops. There should not be any # time delays inside this module, because a module does not have a concept of fixed time delays. If you want the d2 pin to be driven from ~q2, then you just assign it as such:

assign d2 = ~q2

Because in hardware, this is just a wire looping back from the output of ~q2 back to d2. It always exists, and it has no concept of time.

As to specifically why you're getting X's on your output, I'll guess that it comes from the flip flop design you posted in your last question. 

module DFlipFlop(d,q,clk);

input d,clk;
output q;

assign q = clk?( (d==1)? 1:0) : q;

endmodule

This is not a flip flop, as there is no state retention here, it's just an assign statement with an infinite feedback loop, (you essentially just have a wire driving itself).

If you want to model a flip flop, you need to use an always @(posedge clk) block, to imply that you want some state retention. I'll leave it to you to look up how to use an always block to model a flip flop.

Tim
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