Arithmetic operations on integers in vhdl

Question

I'm trying to do a few mathematical operations on integers in a piece of vhdl code but when i try to compile the tool says "0 definitions of operator "+" match here". Here is what i'm trying to do:

for i in 0 to arr_size - 1 loop
   for j in 0 to arr_size - 1 loop
      for k in 0 to arr_size - 1 loop
         for l in 0 to arr_size - 1 loop
            for m in 0 to arr_size - 1 loop
               mega_array(i)(j)(k)(l)(m) <= i*(arr_size**4) + j*(arr_size**3) + k*(arr_size**2) + l*(arr_size**1) + m*(arr_size**0);
            end loop;
         end loop;
      end loop;
   end loop;
end loop;

The problem was encountered in the line where mega_array is set. Note that this whole block is in a process.

Additionally:

arr_size : integer := 4;
sig_size : integer := 32

type \1-line\ is array (arr_size - 1 downto 0) of unsigned (sig_size - 1 downto 0);
type square is array (arr_size - 1 downto 0) of \1-line\;
type cube is array (arr_size - 1 downto 0) of square;
type hypercube is array (arr_size - 1 downto 0) of cube;
type \5-cube\ is array (arr_size - 1 downto 0) of hypercube;

signal mega_array : \5-cube\;

The problem is likely to be in the Library/Use clauses or the declaration of mega_array; it would be worth adding them to the question. "0 definitions match" often means there are 2 or more visible (ambiguous) definitions because you have too many overlapping "Use" clauses. — , Feb 18 '13 at 13:37

score 2 · Accepted Answer · edited Feb 18 '13 at 14:35

2

When reading your older post, the mega_array is an array of 4 levels with at the lowest level an unsigned. In your code in this question I see 5 levels. So at the fifth level you have bit. You can not assign an integer to a std_logic.

Could it be this code is what you want?

    for i in 0 to arr_size - 1 loop                -- 5-cube
        for j in 0 to arr_size - 1 loop            -- hypercube
            for k in 0 to arr_size - 1 loop        -- cube
                for l in 0 to arr_size - 1 loop    -- square
                   for m in 0 to arr_size - 1 loop -- 1-line
                      mega_array(i)(j)(k)(l) <= to_unsigned(i*(arr_size**4) + j*(arr_size**3) + k*(arr_size**2) + l*(arr_size**1), 32);
                   end loop
                end loop;
            end loop;
        end loop;
    end loop;

The to_unsigned functions converts the integer to an unsigned, what is the type of 1-line. The second parameter is the size of the vector to convert the integer into. It must be the same as the size of 1-line.

edited Feb 18 '13 at 14:35

Jean-Luc Nacif Coelho

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answered Feb 18 '13 at 13:44

vermaete

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it says it expects the type "std_ulogic" for to_unsigned – Jean-Luc Nacif Coelho Feb 18 '13 at 13:58
In the code you have posted, IMHO there is still one loop too much. Within the 'm' loop you're at bit level of the `unsigned`. And at this bit you try to assign a integer (with the coversion to 'unsigned'). IMHO, you don't need the 'm' level. Assign you're calculated value at the 'l' level. – vermaete Feb 18 '13 at 14:13
You forgot the "hypercube" level. – Jean-Luc Nacif Coelho Feb 18 '13 at 14:13
bit -> 1-line (32 bit unsigned) -> square -> cube -> 5-cube. Hypercube and 5-cube have the same type. I don't see that Hypercube is used. Mega_array is of type 5-cube. – vermaete Feb 18 '13 at 14:20
Yea that's wrong. A 5-cube is an array of hypercube. PS: That was the problem lol. – Jean-Luc Nacif Coelho Feb 18 '13 at 14:30

Arithmetic operations on integers in vhdl

1 Answers1