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I am trying to simulate my VHDL file, but am running into the following error:

# ** Error: (vcom-11) Could not find work.lab1.
# 
# ** Error: (vcom-1195) Cannot find expanded name "work.lab1".
# 
# ** Error: Unknown expanded name.
# ** Error: VHDL Compiler exiting
# ** Error: c:/altera/12.1/modelsim_ase/win32aloem/vcom failed.
# Error in macro ./DE2_TOP_run_msim_rtl_vhdl.do line 8
# c:/altera/12.1/modelsim_ase/win32aloem/vcom failed.
#     while executing
# "vcom -93 -work work"

I compiled the code successfully through both Quartus II and the ModelSim compiler before attempting to simulate. I do have a lab1 entity and architecture in my code (I can even see it in the Design Units tab of the Quartus Project Navigator), so I don't really understand this error. Anyone know what's causing this?

John Roberts
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    try this: 1) vlib work; 2) vmap work work; 3) vcom _the_lab1_file; 4) vcom _the_toplevel_file; 4) vsim work._the_toplevel_entity – vermaete Jan 26 '13 at 17:41
  • Thanks, that worked. So do I have to type all that every time now? My lab1 and top level entity are also in the same file, so I assume that I can combine steps 3 and 4, right? – John Roberts Jan 26 '13 at 17:46
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    'vlib' is to create a library. 'vmap' is to bind the directory 'work' to the VHDL library 'work' (check the modelsim.ini file). Vcom is to compile the VHDL code ('vlog' for Verilog). And 'vsim' to start the simulator. What you have to run depends on what already exists in your project (=simulation directory). But most of the times it only 'vcom' when you changed your source code and 'vsim' to simulate. But all these things can be done in the GUI too. – vermaete Jan 26 '13 at 17:52
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    I would keep one VHDL file for every entity/architecture combination. – vermaete Jan 26 '13 at 17:53

1 Answers1

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When the simulator is compiling the toplevel (DE2_TOP) it want to know how the used components are like. So, you should have compiled the lowerlevel components before compiling the upperlevel components.

What I do most of the times to fix this is compiling all components in correct order and then use the 'vmake' ('vmake -work work > work.vmake') command of Modelsim to generate a makefile out of the library (work). Once you have the makefile you can execute it with (make -f work.vmake). And all files will be compiled in order.

Note: Verilog is much more relaxed in those things...

vermaete
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  • Thanks for this great answer. On a somewhat related note, do you know what a value of "U" means in the Objects window of the ModelSim output? I am trying to simulate button presses on my four FPGA buttons by initializing in my lab1 entity like this: "key : in std_logic_vector(3 downto 0) := "0010";". However, even after doing this, ModelSim still gives me a value of "U" for each of my keys. Any idea why? – John Roberts Jan 26 '13 at 17:59
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    You better make a new question about it with some code. But the 'U' is the 'uninitialized' state of the 'std_logic' type. It's a signal that doesn't has been set yet. – vermaete Jan 26 '13 at 18:09
  • I have posted it as a new question here: http://stackoverflow.com/questions/14540139/modelsim-simulating-button-presses – John Roberts Jan 26 '13 at 18:31