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I am making a program to display the no. of days in the month provided by user. I am making this program at Data Flow level. As I am new to verilog, I don't know if we can use if/else conditions or case statement in data flow level. because using if/else statement will make this program piece of cake. If not how can I implement the following idea in data flow level.

if(month==4 || month==6 || month==9|| month==11)

      days=30;
 else
    if(month==2 && leapyear==1)
        days=29;

Here is my verilog incomplete code:

 module LeapYear(year,month,leapOrNot,Days);

 input year,month;

 output leapOrNot,Days;



 //if (year % 400 == 0) || ( ( year % 100 != 0) && (year % 4 == 0 ))
 leapOrNot=((year&400)===0) && ((year % 100)!==0 || (year & 4)===0);

  Days=((month & 4)===4 ||(month & 6)===6 ||(month & 9)===9 ||(month & 11)===11 )
dwikle
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Alfred
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    You should probably read a tutorial like : http://www.asic-world.com/verilog/veritut.html, as you seem to have a very poor grasp on the fundamentals. You should try to understand the language better before you start trying to write modules. – Tim Dec 18 '12 at 22:17

1 Answers1

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You cannot use if/else in a continuous assignment, but you can use the conditional operator, which is functionally equivalent.

Try this:

assign Days = (month == 4 || month == 6 || month == 9 || month == 11) ? 30 : 
              (month == 2 && leapyear == 1) ? 29;

That will produce what you put in your question. But's its not the correct answer as you are missing the conditions where Days is equal to 28 or 31.

EDIT: Here's how to combine all the conditions into a single assign statement using the conditional operator.v

assign Days = (month == 4 || month == 6 || month == 9 || month == 11) ? 30 : 
              (month == 2 && leapyear == 1) ? 29 :
              (month == 2 && leapyear == 0) ? 28 :
              31;
dwikle
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  • I am getting `illegal refrence error` for this code: assign leapOrNot=((year % 400) == 0 || (year % 100) != 0 && (year % 4) == 0) ? 1:0; assign Days = (month == 4 || month == 6 || month == 9 || month == 11) ? 30 :31; assign Days = (month == 2 && leapOrNot == 1) ? 29:28; – Alfred Dec 20 '12 at 03:51
  • It's not clear if this is the source of your error, but you cannot assign Days twice in two assign statements. You need to combine all the conditions into a single assigns statement. I will update my answer to show how this is done. – dwikle Dec 20 '12 at 04:01
  • I don't think assigning days twice is a problem cuz only one conditional operator of days assignment will be active at a time. I am still getting `Register is illegal in left-hand side of continuous assignment` – Alfred Dec 20 '12 at 04:07
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    That's not how Verilog works... the assingments are always active so you cannot have two assignments to the same net. On the latest error, you cannot place a continuous assignment on a register. Try changing it to a `wire`. Or change from a continuous assignment to procedural assignment in an `always` block, as was suggested on the same question on electronics.stackexchange.com – dwikle Dec 20 '12 at 04:18
  • LeapOrNot and Days both are declared as wires – Alfred Dec 20 '12 at 04:21
  • I have another question. Can we use `assign` for both `reg` and `wire` – Alfred Dec 20 '12 at 04:23
  • No, you cannot use `assign` on a `reg`. That is what the error you got is saying: `Register is illegal in left-hand side of continuous assignment` – dwikle Dec 20 '12 at 04:32