VHDL Entity not executing in simulator with unassigned 'U' inputs

Question

I've run into this problem in a few places, and my best guess for why I am getting no output from a design entity (in this case a 4:1 mux) is that one of the inputs was unassigned (U's).

So pretend this Mux is embedded within a lot of other structures, so I can't just Force the inputs to whatever I want, sometimes some of them will have nothing driving them.

Say: input 0 = "111111111111111"

but: input 3 = "UUUUUUUUUUUUUUUU"

and all I want is to output input0 (c0 = c1 = 0), so input3 shouldn't matter logically

I still get

output = "UUUUUUUUUUUUUUUU" (default value)

Also, there are no errors in the compilation or running.

Here's the code:

USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY Mux4to1 IS
  GENERIC (size : POSITIVE := 16);   -- Size of the input
  PORT (input0, input1, input2, input3 : IN std_logic_vector (size-1 DOWNTO 0);
    output: OUT std_logic_vector (size-1 DOWNTO 0); 
    control0, control1 : IN std_logic ); 
END ENTITY Mux4to1;

--
ARCHITECTURE Behavior OF Mux4to1 IS
BEGIN
   PROCESS ( input0, input1, input2, input3, control0, control1 )
    BEGIN
        IF (control0 = '0') THEN
          IF (control1 = '0') THEN     -- Enable 00
            output <= input0;
          ELSIF(control1 = '1')THEN       -- Enable 10
            output <= input2;
          END IF;
        ELSIF (control0 = '1') THEN
          IF (control1 = '0') THEN     -- Enable 01
            output <= input1;
          ELSIF(control1 = '1')THEN      -- Enable 11
            output <= input3;
          END IF;
        END IF;
  END PROCESS; 
END ARCHITECTURE Behavior;

What can I do to get around this mess?

First, check your best guess. Simulate this mux on its own, and verify that when you drive `input3 <= (others => '0')` it works as expected, and `input3 <= (others => 'U')` breaks it again. — , Dec 05 '12 at 10:43

score 0 · Accepted Answer · answered Dec 05 '12 at 11:40

You're not driving output for every single option of control0 and control1. If either of them is not a 0 or 1 (they may be U at the start of the simulation too) you won't end up driving output.

There are a variety of solutions...

One is to be less explicit:

  IF (control0 = '0') THEN
          IF (control1 = '0') THEN     -- Enable 00
            output <= input0;
          ELSE                         -- Enable 10
            output <= input2;
          END IF;
        ELSE
          -- etc

Or if you really want to do something different (like report a warning), add an else after each elsif clause to catch those options and a report.

VHDL Entity not executing in simulator with unassigned 'U' inputs

1 Answers1