Verilog HDL Negate Monitor Variable

Question

I am teaching myself Verilog HDL as of today and attempting to understand. I am trying to display the opposite/negation of a variable in bit form that is passing through a logic diagram example.

module My_Implementation();
reg A,B,C,D;
wire F;

assign F = ((A&&(!B))||((!A)&&B))&&(C||(!D));

initial begin
    $monitor("A=%b A'=%b B=%b B'=%b C'=%b D=%b OUTPUT=%b",A,!A,B,!B,!C,D,F);
    #10     A=0; B=0; C=0; D=0;
    #10     A=1;
    #10     B=1;
    #10     C=1;
    #10     D=1;
    #10     A=0;
    #10     B=0;
    #10     C=0;
    #10     D=0;
    #10     $finish;
end

endmodule

I've tried numerous combinations to try to get the negated variable to display but I only get the output of "X".

Morgan · Answer 1 · 2012-12-04T14:25:03.970

I copied and pasted your example and ran it with my simulator it output:

A=x A'=x B=x B'=x C'=x D=x OUTPUT=x
A=0 A'=1 B=0 B'=1 C'=1 D=0 OUTPUT=0
A=1 A'=0 B=0 B'=1 C'=1 D=0 OUTPUT=1
A=1 A'=0 B=1 B'=0 C'=1 D=0 OUTPUT=0
A=1 A'=0 B=1 B'=0 C'=0 D=0 OUTPUT=0
A=1 A'=0 B=1 B'=0 C'=0 D=1 OUTPUT=0
A=0 A'=1 B=1 B'=0 C'=0 D=1 OUTPUT=1
A=0 A'=1 B=0 B'=1 C'=0 D=1 OUTPUT=0
A=0 A'=1 B=0 B'=1 C'=1 D=1 OUTPUT=0
A=0 A'=1 B=0 B'=1 C'=1 D=0 OUTPUT=0

If we add time into the report, we can see that the x happens at time 0 before anything has been declared. I would expect this and it resolves as soon as all the inputs have been defined. It might be worth noting for those new to Verilog that x implies an unknown value.

$monitor("%2t : A=%b A'=%b B=%b B'=%b C'=%b D=%b OUTPUT=%b",$realtime, A,!A,B,!B,!C,D,F);

New Output:

 0 : A=x A'=x B=x B'=x C'=x D=x OUTPUT=x
10 : A=0 A'=1 B=0 B'=1 C'=1 D=0 OUTPUT=0
20 : A=1 A'=0 B=0 B'=1 C'=1 D=0 OUTPUT=1
30 : A=1 A'=0 B=1 B'=0 C'=1 D=0 OUTPUT=0
40 : A=1 A'=0 B=1 B'=0 C'=0 D=0 OUTPUT=0
50 : A=1 A'=0 B=1 B'=0 C'=0 D=1 OUTPUT=0
60 : A=0 A'=1 B=1 B'=0 C'=0 D=1 OUTPUT=1
70 : A=0 A'=1 B=0 B'=1 C'=0 D=1 OUTPUT=0
80 : A=0 A'=1 B=0 B'=1 C'=1 D=1 OUTPUT=0
90 : A=0 A'=1 B=0 B'=1 C'=1 D=0 OUTPUT=0

I've tweaked my monitor to display the correct timeline. However, when I run my code which is the same as you ran. All the negated variables still return x. This is even after the initial undeclared at 10,20,30,etc... Could it be the compiler I am using? I am currently using iverilog. — Lakeside, Dec 04 '12 at 19:39
I think it might be the compiler/simulator you are using, try `assign F = ((A&&(B==0))||((A==0)&&B))&&(C||(D==0));` or instead of `!A` (not A) try `~A` (invert A) in your monitor statement. — Morgan, Dec 05 '12 at 08:46

Verilog HDL Negate Monitor Variable

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