I am a beginner with Verilog HDL and trying to model a few modules from logic diagrams. If two wires are input into a NAND gate followed by another inverter afterwards, would that just be a AND gate in theory? Since the output wire desired is on the other side of the inverter. Would it be.
AND
g1(F,A,B)
A and B being the inputs and F being the output. Also, just for future knowledge, how would I implement an inverter using Verilog?
To answer your first question, yes, a NAND gate followed by an inverter is logically equivalent to an AND gate.
On your second question, the normal way to invert a signal in Verilog would be to use the bit-wise negation operator: ~
wire A;
assign A = ~B; // A is "not B"
Since you are asking about modeling simple logic using Verilog gate primitives, I will add that there is a primitive for an inverter called not.
not U1(A, B); // A is "not B"
Here is a good reference on Verilog gate primitives.
