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I am working on a MIPS32 like CPU and I am wondering how the MIPS32 exception and interrupt handling works exactly. The MIPS32 Privileged Resource Architecture guide doesn't give much information. I am wondering about several things which are:

  1. What happens if there is an exception or interrupt in an exception or interrupt handler?

  2. MIPS32 has 5 hardware interrupts and 2 software interrupts in the cause register. Are the software interrupts exceptions or are exceptions just shown in the exception code value?

  3. Is there a different interrupt and exception vector?

  4. What happens if there are 2 exceptions that go off in the pipeline before it clears itself for the exception? For example there is an overflow exception followed by another exception, and an interrupt. What happens?

Links to any useful resources will be appreciated.

marc_s
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Alex
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  • This is about hardware architecture - not a good fit for a **programming-related** Q&A site. Please [study the FAQ](http://stackoverflow.com/faq) and respect it - thanks! – marc_s Nov 25 '12 at 19:21
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    Of course, I found some computer architecture related items here so I though that it would be ok to post on Stackoverflow since there is no stack exchange site that is dedicated for computer architecture. This is somewhat related to programming so I thought it was fine. – Alex Nov 25 '12 at 19:29
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    This is about how hardware and software interact, so it's just fine for stackoverflow. – markgz Nov 26 '12 at 02:09

1 Answers1

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  1. Exception handlers should not re-enable exceptions until after they have saved EPC, SR etc.
  2. The software interrupts are exceptions.
  3. Some MIPS CPUs have been built with different interrupt and exception vectors, but this turns out not to be very useful.
  4. MIPS has precise exceptions: i.e. exceptions appear in instruction sequence and only the first exception in the pipeline will be architecturally visible.

See MIPS Run Linux is the best and most readable reference for MIPS exceptions and the MIPS PRA.

markgz
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    If only the first exception (first as in precise exception first) is visible in the pipeline, shouldn't there only be one software interrupt bit in the cause register. Also thanks for the book suggestion – Alex Nov 26 '12 at 02:32
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    An exception triggered by an instruction in the pipeline (such as an overflow) sets the ExCode field in the cause register, and it does not set the cause.IPx bits. The software interrupt bits (cause.IP0 and IP1) are set by writing to the cause register, and they are entirely unrelated to pipeline exceptions. – markgz Nov 26 '12 at 02:50
  • And then the exception handler will have to recognize that there is an exception by doing a test on the ExCode Field. And one last thing, are interrupts prioritized over exceptions? – Alex Nov 26 '12 at 03:01
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    Yes, interrupts are prioritized over exceptions. See section 6.2.1 in the MIPS PRA specification. – markgz Nov 26 '12 at 03:11
  • Hey, I am wondering about another thing, I read the book and I am wondering on how the IPL is implemented. Is the IPL just the 5 hardware interrupt bits? Does the CPU have hardware that determines if a higher interrupt bit is enabled? Also what happens if you return from an interrupt when there is a unhandled lower priority interrupt that wasn't nested? – Alex Dec 15 '12 at 15:56